Hello,
DSP will be communicating with up to 6 devices on SPI bus I and want to make sure I do not miss anything in hardware design.
TMS320F2837xD data sheet specifies sink/source current as 4mA. GPIO rise/fall time as 8nS
Some slaves are on the separate board = extra connector. Load capacitance may be in the 30p range.
Any suggestion on HW design, like buffering control signals or termination,
reference designs with multiple SPI devices on the bus?
Thank you