TMS320F28075: Trip Zone interrupt not generating

sagar dhavali

Part Number: TMS320F28075
Other Parts Discussed in Thread: C2000WARE

Hello,

I am using comparator submodule to generate a trip, which is connected to ePWM tripzone. I have configured trip as one-shot. I see that OST flag is 1 in TZFLG but INT flag stays at 0. I need the interrupt to be generated so that I can set necessary variables in my ISR. Why interrupt is not getting generated?

Comparator and EPWM initialization.

EALLOW;
/**** Step 1: Enable and configure Compare subsystem. ****/
//Enable CMPSS
Cmpss3Regs.COMPCTL.bit.COMPDACE            = 1;
//NEG signal comes from DAC
Cmpss3Regs.COMPCTL.bit.COMPHSOURCE         = INTERNAL_DAC;
//Use VDDA as the reference for DAC
Cmpss3Regs.COMPDACCTL.bit.SELREF           = REFERENCE_VDDA;
//Set DAC to midpoint for arbitrary reference
Cmpss3Regs.DACHVALS.bit.DACVAL             = 1118;
//Set to typical hysteresis
Cmpss3Regs.COMPHYSCTL.bit.COMPHYS		   = TYPICAL_1x;

/**** Step 2: Configure Digital Filter ****/
//Maximum CLKPRESCALE value provides the most time between samples
Cmpss3Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 0;		// 0 prescale => max resolution (10ns)
//Maximum SAMPWIN value provides largest number of samples
Cmpss3Regs.CTRIPHFILCTL.bit.SAMPWIN        = 13;
//Maximum THRESH value requires static value for entire window
//THRESH should be GREATER than half of SAMPWIN
Cmpss3Regs.CTRIPHFILCTL.bit.THRESH         = 7;

/**** Step 3: Initialize the sample values in the digital FIFO ****/
//Do not use initialization. On reset, all FIFO values would be zeros.
Cmpss3Regs.CTRIPHFILCTL.bit.FILINIT        = 0;

/**** Step 4: Configure CTRIPOUT path ****/	
//Digital filter output feeds CTRIPH and CTRIPOUTH
Cmpss3Regs.COMPCTL.bit.CTRIPHSEL           = CTRIP_FILTER;
Cmpss3Regs.COMPCTL.bit.CTRIPOUTHSEL        = CTRIP_FILTER;

/**** Step 5: Configure ePWM X-bar modules to accept filter output ****/
//Configure TRIP5 to be CTRIP3H
EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX4 = 0;
//Enable TRIP5 Mux for Output
EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX4   = 1;

/**** Step 6: Configure EPWM registers ****/
//Configure EPWM output A & B to go low on trip.
EPwm2Regs.TZCTL.bit.TZA					   = TZ_FORCE_LO;	
EPwm2Regs.TZCTL.bit.TZB					   = TZ_FORCE_LO;
//Configure DCA to be TRIP5
EPwm2Regs.TZDCSEL.bit.DCAEVT1          	   = TZ_DCBH_HI;
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL    	   = 0x4; 			// Trip5
EPwm2Regs.DCAHTRIPSEL.bit.TRIPINPUT5   	   = 0;				// Single trip input; Not ORed
//Configure DCA as OST
EPwm2Regs.TZSEL.bit.DCAEVT1  	           = 1;				// Enable
//Configure DCA path to be unfiltered & async
EPwm2Regs.DCACTL.bit.EVT1SRCSEL            = DC_EVT1;
EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL        = DC_EVT_ASYNC;
// Clear trip flags
EPwm2Regs.TZCLR.bit.OST					   = 1;
EPwm2Regs.TZCLR.bit.INT               	   = 1;
//Enable DCA interrupt
EPwm2Regs.TZEINT.bit.OST	               = 1;
EDIS;

over 8 years ago

0 Baskaran Chidambaram over 8 years ago

TI__Genius 17370 points

Hello,
I am writing to let you know that a C2000 team member has been assigned to this post and should be answering shortly.

Regards
Baskaran

0 Kris Parrent over 8 years ago

TI__Genius 15260 points

Hi Sagar,

Have you enabled the interrupt in the PIE and IER? What are the values of the flags in PIEIFR and IFR? Is this the same application as the other thread here?

Regards,

Kris

0 Gautam Iyer over 8 years ago

Guru 192875 points

Hi Sagar,

Did you checkout this example: C:\ti\c2000\C2000Ware_1_00_01_00\device_support\f2807x\examples\cpu1\epwm_trip_zone\cpu01

Regards,
Gautam

0 sagar dhavali over 8 years ago in reply to Kris Parrent

Intellectual 555 points

Hello Kris,

1. Yes, I have enabled the interrupt in PIE and IER.
2. PIEIFR : 1 and IFR : 0
3. Yes it is the same application. Just the different branch. It is strange that that earlier build worked after I acknowledged PIE interrupt groups for further interrupts and this one not.

Thanks,
Sagar

0 sagar dhavali over 8 years ago in reply to Gautam Iyer

Intellectual 555 points

Hello Gautam,

Yes, I checked out this exampled and followed on the same lines. The only difference is that I don't re-arm the OST again inside the ISR as I would like to shut down the system once I detect the interrupt.

Regards,
Sagar

0 Kris Parrent over 8 years ago in reply to sagar dhavali

TI__Genius 15260 points

Sagar,

In this scenario you're not receiving any interrupts, correct?

Can you post your code enabling the PIE and IER? It sounds like the PWM is properly setup due to the PIEIFR flag getting set. Watch out for things like EALLOW. You may want to check the values in the PIEIER and IER registers to verify the writes took effect.

Regards,

Kris

0 sagar dhavali over 8 years ago in reply to Kris Parrent

Intellectual 555 points

Yes, not receiving any interrupt.

IER |= M_INT1 | M_INT2 | M_INT3 | M_INT8 | M_INT9 | M_INT10 | M_INT11 | M_INT12 | M_INT14; //Enable Interrupts
PieVectTable.EPWM2_TZ_INT = &epwm_PFC_B_B_tzint_isr;
PieCtrlRegs.PIEIER2.bit.INTx2 = 1;   /* EPWM2_TZ */

__interrupt void epwm_PFC_B_B_tzint_isr(void)
{
	if(EPwm2Regs.TZOSTFLG.bit.DCAEVT1)
		tz.tripzone[TRIPZONE_PFC_B_PLUS] = 1;
	else
		tz.tripzone[TRIPZONE_PFC_B_PLUS] = 0;
	
	// Acknowledge this interrupt to receive more interrupts from group 2
	PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;
}

I have not used EALLOW for IER and PieCtrlRegs. Is that the problem? I think these regs are not write protected. Please correct me if I am wrong.

0 Kris Parrent over 8 years ago in reply to sagar dhavali

TI__Genius 15260 points

Sagar,

I confirmed that EALLOW is not required for the the IER and PieCtrlRegs writes. The PieVectTable does require EALLOW. From one of our example codes, here is the applicable code:

EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.EPWM2_TZ_INT = &epwm2_tzint_isr;
EDIS;

How are you determining that the interrupt is not occurring? Are you using a breakpoint or watching the TRIPZONE_PFC_B_PLUS variable? What is the default value of this variable?

Regards,
Kris

0 sagar dhavali over 8 years ago in reply to Kris Parrent

Intellectual 555 points

I do have the EALLOW for PieVectTable.

I am using a breakpoint inside the ISR. That TRIPZONE_PFC_B_PLUS is constant with value of 2. I will look at tz.tripzone array in other routines.

0 Vivek Singh over 8 years ago in reply to sagar dhavali

TI__Guru** 115881 points

Sagar,

Just a quick check. Do you have following code to enable global interrupt after setting IER?

EINT;

Regards,

Vivek Singh

0 sagar dhavali over 8 years ago in reply to Vivek Singh

Intellectual 555 points

Yes, I do.

0 Kris Parrent over 8 years ago in reply to sagar dhavali

TI__Genius 15260 points

Hi Sagar,

In the original post you said "OST flag is 1 in TZFLG but INT flag stays at 0"

Are you referring to the INT flag in the TZFLG register? If this isn't set then the PIEIFR flag should not be set. Can you confirm you were seeing PIEIFR2[INTx2]=1 and TZFLG[INT] = 0?

Regards,
Kris

0 sagar dhavali over 8 years ago in reply to Kris Parrent

Intellectual 555 points

Yes, I was referring to INT flag in the TZFLG register. I was seeing PIEIFR2[INTx2]=1 and TZFLG[INT] = 0.

NOTE: I cannot reproduce the same scenario now. I decided to work on other branch which worked :/

0 Kris Parrent over 8 years ago in reply to sagar dhavali

TI__Genius 15260 points

No problem. If you come back along this issue then just let us know.

0 sagar dhavali over 8 years ago in reply to Kris Parrent

Intellectual 555 points

Sure. I will :)

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TMS320F28075: Trip Zone interrupt not generating