TMS320F28035: Software reset SCI module for many times

Hello,
I am writing to let you know that a C2000 team member has been assigned to this post and should be answering shortly.

Regards
Baskaran

Dear Champs,

I updated the background, but the questions above are the same.

"They add a software SCI reset when there are noises on RX by detecting errors in register SCIRXST, and use LED to indicate if normal SCI interrupt and SCI reset for errors happens.

When they put their system in a noisy environment, they found there were software SCI resets as expected in the beginning.

However, when they tested the system for a very long time (several hours), it appeared SCI hanged (no more TX, during continuous RX from PC), but other functions like PWM of C2000 still worked normally. Even when they changed the environment from noisy to non-noisy, the SCI still hanged because there was no SCI ISR.
It is expected that SCI module should be reset again and again after noise and then SCI should work normally."


Therefore, we have questions and need your support to clarify this issue:

1) How do we correctly "reset SCI"?

So far, we reset SCI as below:

EALLOW;
SciaRegs.SCICTL1.bit.RXENA =0;
SciaRegs.SCICTL1.bit.TXENA =0;
SciaRegs.SCICTL2.bit.RXBKINTENA =0;
SciaRegs.SCICTL2.bit.TXINTENA =0;
PieCtrlRegs.PIEIER9.bit.INTx1=0;
PieCtrlRegs.PIEIER9.bit.INTx2=0;
SysCtrlRegs.PCLKCR0.bit.SCIAENCLK=0;
EDIS;

After 300 ms, we then enable it.
EALLOW;
SciaRegs.SCIRXST.bit.RXRDY=0;
SciaRegs.SCICTL2.bit.TXRDY=0;
PieCtrlRegs.PIEIER9.bit.INTx1=1;
PieCtrlRegs.PIEIER9.bit.INTx2=1;
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP9;

SysCtrlRegs.PCLKCR0.bit.SCIAENCLK=1;
SciaRegs.SCICTL1.bit.SWRESET=0;
SciaRegs.SCICTL1.bit.SWRESET=1;
SciaRegs.SCICTL2.bit.RXBKINTENA=1;
SciaRegs.SCICTL1.bit.RXENA =1;
SciaRegs.SCICTL1.bit.TXENA =1;
EDIS;


2) Is there any problem or concern if we reset SCI module for many times?


3) When we reset SCI module, are RX buffer and SCIRXST cleared as well?



Wayne

Edit 8/7/17

Point 3 below should read: 3. The RX buffer is not reset by SCICTL1.bit.SWRESET, however SCIRXST will be reset... Both are reset by a system reset.

Regards,
Cody

__________________________________________________________________

Wayne,

1. I don't see anything obviously wrong with this code.
2. No, there are no issues with many resets of the SCI module.
   
   1. If you are sending continuous data and reset the SCI module, it will likely come up half way through a frame and cause an immediate framing error, this would then cause you to have to reset the SCI module again. You can avoid issues like this by preforming some hand shaking between the devices.

3. Yes, they are reset.

Regards,
Cody

Cody,

Thank you for your information.
We are debugging it towards if there is any SCI interrupt flag which somehow was raised unexpectedly.

About reset, would you please help us clarify reset by SWRESET (SciaRegs.SCICTL1.bit.SWRESET), SysCtrlRegs.PCLKCR0.bit.SCIAENCLK, and system reset (by watchdog, BOR, POR)?

- Use SW RESET (SciaRegs.SCICTL1.bit.SWRESET) only reset those status bits documented (i.e. TXRDY, TXEMPTY, RXWAKE, PE, PE, FE, BRKDT, RXRDY, RX ERROR) are reset, but neither SCI configuration bits nor data buffer (RX buffer, TX buffer) are reset.

- Use SysCtrlRegs.PCLKCR0.bit.SCIAENCLK only stop and then resume SCI module clock, but it will not affect the content of SCI module. That is, all registers are not reset to default values.

- Use system reset (by watchdog, BOR, POR) can totally reset all registers of SCI.

Is my understanding above correct?


Wayne

Cody,

Thank you for your clarification.
We already found a way to solve it.
Thank you.


Wayne

Hello Wayne,

congatulation for solving the problem.

Joachim,

I am not sure if our situations are same or similar.

It may depends on how you trigger your SCI interrupt.

In our case, we originally had thought SWRESET reset all registers inlcuidng Tx/Rx buffers until we realized it only reset some registers (mentioned above).

Note that Tx and Rx buffers are not cleared.

It's possible they will trigger an interrupt again unexpectedly without proper ack so that no more interrupt can be triggered or serviced.

You may check if SCI INT flag is set unexpectedly while SCI seems hanged.

Also, you may try to clear Tx/Rx buffers based on your application properly and see if this helps.

Wayne