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TMS320F28335: WDINT Watchdog

Strong ZHANG
Expert 4500 points
Part Number: TMS320F28335


In our user guide for watchdog, it says that If the watchdog is configured to assert an interrupt, then the WDINT signal will be driven low for 512
OSCCLK cycles, causing the WAKEINT interrupt in the PIE to be taken if it is enabled in the PIE module.

That means WDINT signal will return to be high after 512 OSCCLK cycles, but if disable the watchdog during the 512 OSCCLK cycles, WDINT signal will always keep low and never return to be high.

Here is the code of disalbing the watchdog:

EALLOW;

SysCtrlRegs.WDCR= DISABLE_WATCHDOG;

EDIS;

if add a delay function before disabling the watchdog which work longer than 512 OSCCLK  cycles, then it has no this issue.

so question is why WDINT signal will always keep low if disable the watchdog within 512 OSCCLK cycles.

  • 0
    TI__Genius 17370 points
    Hello,
    I am writing to let you know that a C2000 team member has been assigned to this post and should be answering shortly.

    Regards
    Baskaran
  • 0
    TI__Guru** 115881 points

    Hi Zhang,

    so question is why WDINT signal will always keep low if disable the watchdog within 512 OSCCLK cycles.

    User should not change the WD configuration when WDINT is active. How are you observing that WDINT is not going high again? 

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Expert 4500 points
    Use the while code and GPIO output to generate the signal:

    while(1)
    {
    if(SysCtrlRegsSCSR & 0x04)
    {
    LEDSET;
    }
    else
    {
    LEDCLEAR;
    }
    }

    But it seem that the user guide don't mention it that "User should not change the WD configuration when WDINT is active", including disabling the WD.

    It do mention that when the WDINT is still active low, it should not re-configured from interrupt mode to reset mode. so if disabling the WD when WDINT is active, then it will be impossible to re-configured from interrupt mode to reset mode since the WDINT is always low.

    "If the watchdog is re-configured from interrupt mode to reset mode while WDINT is still active low, then the device will reset immediately. The WDINTS bit in the SCSR register can be read to determine the current state of the WDINT signal before reconfiguring the watchdog to reset mode."
  • 0 in reply to Strong ZHANG
    TI__Expert 4500 points
    Hi Vivek，

    If the User should not change the WD configuration when WDINT is active，which as long as 512 OSCCLK cycles, so when the WD overflow, then it will generate a WD interrupt if configured interrupt mode, and in the WD interrupt the user still should not disable the WD.

    customer wonder if we have an explaination about this and what can be configured for WD in WD interrupt.