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TMS320F28075: VDD current consumption for TMS320F28075

Rahul Ramachandran
Prodigy 740 points
Part Number: TMS320F28075

From latest datasheet of TMS320F28075PZP DSP device, we noticed that the current consumption table got updated. Please see table 5-2 in datasheet for updated current consumption table with internal VREG enabled. From this table we could not get the VDD current consumption. With 340mA IDDIO current consumption we’re failing the Tjmax of the device limits. Please could you help us to get the worst case maximum current consumption split between VDDIO and VDD voltages. These details required for hold-up capacitor computations in our application.

 

 

  • 0
    TI__Genius 17370 points
    Hello,
    I am writing to let you know that a C2000 team member has been assigned to this post and should be answering shortly.

    Regards
    Baskaran
  • 0
    TI__Guru* 95315 points

    The Vdd current will be in the vicinity of the number shown in table 5-1. Note that the number shown in Table 5-2 is not equal to Idd+Iddio numbers from table 5-1. This is because there will be some losses in the internal VREG and also the current drawn by the Vdd rail (in the VREG enabled case) is dependent on the internal VREG trim.

    Please let us know how you computed Tj(max) and also throw some light on the hold-up capacitor requirements.

  • 0 in reply to Hareesh Janakiraman
    TI__Guru* 95315 points
    If, by "hold-up", you are referring to the decoupling capacitor requirements, the numbers are there in the datasheet.
  • 0 in reply to Hareesh Janakiraman
    TI__Prodigy 740 points

    I understand that table-1 represents when we fed power to VDD externally. Table-2 represents the current consumption when we use internal Vdd rail by enabling VREG (by externally grounding the VREGENZ pin).

     

    I would like to understand how Vdd rail get power. From Table-2 my understanding is that it gets power VDDIO which we apply externally. Please confirm.

     

    I do agree that internal VREG has got its own losses. That’s why I have requested current consumption split between VDDIO rail and VDD when we use internal VREG option. Please could you provide these details.

     

    Based on this we’ll compute the total power dissipation, then Tjmax using standard formula.

     

    We’re using external hold-up capacitor (this is not the decap) to power DSP during external power interrupts conditions.

  • 0 in reply to Rahul Ramachandran
    TI__Guru* 95315 points

    From Table-2 my understanding is that it gets power from VDDIO which we apply externally. Please confirm.

    Answer--> Confirmed.

     

    That’s why I have requested current consumption split between VDDIO rail and VDD when we use internal VREG option. Please could you provide these details.

    Answer--> The split happens internal to the device. It is not possible to measure this. I don’t quite understand why information from Table 5-1 cannot be used with some margin. Also, for the purpose of Tj(max), it is the total device power that is important.

  • 0 in reply to Hareesh Janakiraman
    TI__Prodigy 740 points
    Thanks for confirming details.
    If we take 340 mA is total current then, 340 mA x 3.3V = 1.122 Watts. Please let us know if this true? Because if Core current consumption is more than IO current consumption, then it may not be true. Because core operates at 1.2V rail. That’s why we’re asking split. In that case power dissipation = VDD x Idd + VDDIO X Iddio.
    Need your support to get this value. Otherwise we’ll fail in meeting the device Tj values.