Hi,
I'm trying to make spwm using lookup table and epwm interrupt. When counter equals to zero the interrupt generates and it must update the CMPA and CMPB of EPWM1,2 and 3.
When I watch the epwm output ports, it shows that the value of CMPx is the first value in lookup tables and it doesn't update.
(EPWM1:CMPA=CMPB=25, EPWM2:CMPA=CMPB=4675, EPWM3:CMPA=CMPB=4675).
The following is the written program:
/*
* main.c
*/
#include "DSP2833x_Device.h"
#include "DSP2833x_Examples.h"
#include "DSP2833x_Gpio.h"
#include "DSP2833x_EPwm.h"
#include "c2000_main.h"
#include <stdlib.h>
#include <stdio.h>
int i = 0;
Uint16 lut1[240]={25,26,29,35,42,52,63,77,93,111,131,153,177,203,231,261,293,327,363,401,
440,482,525,570,617,666,716,768,821,876,933,991,1051,1112,1174,1238,1303,1369,1437,1505,
1575,1646,1718,1790,1864,1939,2014,2090,2167,2245,2323,2401,2480,2560,2640,2720,2801,2882,2963,3044,
3125,3206,3287,3368,3449,3530,3610,3690,3770,3849,3927,4005,4083,4160,4236,4311,4386,4460,4532,4604,
4675,4745,4813,4881,4947,5012,5076,5138,5199,5259,5317,5374,5429,5482,5534,5584,5633,5680,5725,5768,
5810,5849,5887,5923,5957,5989,6019,6047,6073,6097,6119,6139,6157,6173,6187,6198,6208,6215,6221,6224,
6225,6224,6221,6215,6208,6198,6187,6173,6157,6139,6119,6097,6073,6047,6019,5989,5957,5923,5887,5849,
5810,5768,5725,5680,5633,5584,5534,5482,5429,5374,5317,5259,5199,5138,5076,5012,4947,4881,4813,4745,
4675,4604,4532,4460,4386,4311,4236,4160,4083,4005,3927,3849,3770,3690,3610,3530,3449,3368,3287,3206,
3125,3044,2963,2882,2801,2720,2640,2560,2480,2401,2323,2245,2167,2090,2014,1939,1864,1790,1718,1646,
1575,1505,1437,1369,1303,1238,1174,1112,1051,991,933,876,821,768,716,666,617,570,525,482,
440,401,363,327,293,261,231,203,177,153,131,111,93,77,63,52,42,35,29,26};
Uint16 lut2[240]={4675,4604,4532,4460,4386,4311,4236,4160,4083,4005,3927,3849,3770,3690,3610,3530,3449,3368,3287,3206,
3125,3044,2963,2882,2801,2720,2640,2560,2480,2401,2323,2245,2167,2090,2014,1939,1864,1790,1718,1646,
1575,1505,1437,1369,1303,1238,1174,1112,1051,991,933,876,821,768,716,666,617,570,525,482,
440,401,363,327,293,261,231,203,177,153,131,111,93,77,63,52,42,35,29,26,
25,26,29,35,42,52,63,77,93,111,131,153,177,203,231,261,293,327,363,401,
440,482,525,570,617,666,716,768,821,876,933,991,1051,1112,1174,1238,1303,1369,1437,1505,
1575,1646,1718,1790,1864,1939,2014,2090,2167,2245,2323,2401,2480,2560,2640,2720,2801,2882,2963,3044,
3125,3206,3287,3368,3449,3530,3610,3690,3770,3849,3927,4005,4083,4160,4236,4311,4386,4460,4532,4604,
4675,4745,4813,4881,4947,5012,5076,5138,5199,5259,5317,5374,5429,5482,5534,5584,5633,5680,5725,5768,
5810,5849,5887,5923,5957,5989,6019,6047,6073,6097,6119,6139,6157,6173,6187,6198,6208,6215,6221,6224,
6225,6224,6221,6215,6208,6198,6187,6173,6157,6139,6119,6097,6073,6047,6019,5989,5957,5923,5887,5849,
5810,5768,5725,5680,5633,5584,5534,5482,5429,5374,5317,5259,5199,5138,5076,5012,4947,4881,4813,4745};
Uint16 lut3[240]={4675,4745,4813,4881,4947,5012,5076,5138,5199,5259,5317,5374,5429,5482,5534,5584,5633,5680,5725,5768,
5810,5849,5887,5923,5957,5989,6019,6047,6073,6097,6119,6139,6157,6173,6187,6198,6208,6215,6221,6224,
6225,6224,6221,6215,6208,6198,6187,6173,6157,6139,6119,6097,6073,6047,6019,5989,5957,5923,5887,5849,
5810,5768,5725,5680,5633,5584,5534,5482,5429,5374,5317,5259,5199,5138,5076,5012,4947,4881,4813,4745,
4675,4604,4532,4460,4386,4311,4236,4160,4083,4005,3927,3849,3770,3690,3610,3530,3449,3368,3287,3206,
3125,3044,2963,2882,2801,2720,2640,2560,2480,2401,2323,2245,2167,2090,2014,1939,1864,1790,1718,1646,
1575,1505,1437,1369,1303,1238,1174,1112,1051,991,933,876,821,768,716,666,617,570,525,482,
440,401,363,327,293,261,231,203,177,153,131,111,93,77,63,52,42,35,29,26,
25,26,29,35,42,52,63,77,93,111,131,153,177,203,231,261,293,327,363,401,
440,482,525,570,617,666,716,768,821,876,933,991,1051,1112,1174,1238,1303,1369,1437,1505,
1575,1646,1718,1790,1864,1939,2014,2090,2167,2245,2323,2401,2480,2560,2640,2720,2801,2882,2963,3044,
3125,3206,3287,3368,3449,3530,3610,3690,3770,3849,3927,4005,4083,4160,4236,4311,4386,4460,4532,4604};
interrupt void epwm1_timer_isr(void)
{
EPwm1Regs.CMPA.half.CMPA = lut1[i];
EPwm1Regs.CMPB = lut1[i];
EPwm2Regs.CMPA.half.CMPA = lut2[i];
EPwm2Regs.CMPB = lut2[i];
EPwm3Regs.CMPA.half.CMPA = lut3[i];
EPwm3Regs.CMPB = lut3[i];
i++;
if(i == 240) i=0;
EPwm1Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
void main(void)
{
InitSysCtrl();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
EALLOW;
PieVectTable.EPWM1_INT = &epwm1_timer_isr;
EDIS;
IER |= M_INT3;
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
EINT;
ERTM;
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Stop all the TB clocks
EDIS;
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // EPWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // EPWM1B
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // EPWM2A
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // EPWM2B
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // EPWM3A
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // EPWM3B
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enabling Pull-up
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0;
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0;
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0;
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0;
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0;
EDIS;
EPwm1Regs.TBPRD = 6250;
EPwm1Regs.TBCTR = 0x0000;
EPwm1Regs.TBCTL.bit.CTRMODE = 2; // Up-Down
EPwm1Regs.TBCTL.bit.SYNCOSEL = 3; // Disable
EPwm1Regs.TBCTL.bit.PHSDIR = 0;
EPwm1Regs.TBCTL.bit.PHSEN = 0; // Disable
EPwm1Regs.TBCTL.bit.CLKDIV = 0; // /1
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // /1
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0; // Shadow Mode
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm1Regs.CMPCTL.bit.LOADAMODE = 0; // Load on CTR=Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;
EPwm1Regs.CMPA.half.CMPA = 0;
EPwm1Regs.CMPB = 0;
EPwm1Regs.AQCTLA.all = 144; // Set on CAD, Clear on CAU
EPwm1Regs.AQCTLB.all = 1536; // Set on CBU, Clear on CBD
EPwm1Regs.AQCSFRC.bit.CSFA = 0; // Disable
EPwm1Regs.AQCSFRC.bit.CSFB = 0; // Disable
EPwm1Regs.AQSFRC.bit.RLDCSF = 0; // Load on CTR=Zero
EPwm1Regs.DBCTL.bit.OUT_MODE = 3;
EPwm1Regs.DBCTL.bit.IN_MODE = 0;
EPwm1Regs.DBCTL.bit.POLSEL = 2;
EPwm1Regs.DBFED = 10;
EPwm1Regs.DBRED = 10;
EPwm1Regs.ETSEL.bit.SOCAEN = 0; // Disable
EPwm1Regs.ETSEL.bit.SOCBEN = 0; // Disable
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable
EPwm1Regs.ETSEL.bit.INTSEL = 1; // CTR=Zero
EPwm1Regs.ETPS.bit.INTPRD = 1; // First Event
EPwm2Regs.TBPRD = 6250;
EPwm2Regs.TBCTR = 0x0000;
EPwm2Regs.TBCTL.bit.CTRMODE = 2;
EPwm2Regs.TBCTL.bit.SYNCOSEL = 3;
EPwm2Regs.TBCTL.bit.PHSDIR = 0;
EPwm2Regs.TBCTL.bit.PHSEN = 0;
EPwm2Regs.TBCTL.bit.CLKDIV = 0;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm2Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm2Regs.CMPCTL.bit.LOADBMODE = 0;
EPwm2Regs.CMPA.half.CMPA = 0;
EPwm2Regs.CMPB = 0;
EPwm2Regs.AQCTLA.all = 144;
EPwm2Regs.AQCTLB.all = 1536;
EPwm2Regs.AQCSFRC.bit.CSFA = 0;
EPwm2Regs.AQCSFRC.bit.CSFB = 0;
EPwm2Regs.AQSFRC.bit.RLDCSF = 0;
EPwm2Regs.DBCTL.bit.OUT_MODE = 3;
EPwm2Regs.DBCTL.bit.IN_MODE = 0;
EPwm2Regs.DBCTL.bit.POLSEL = 2;
EPwm2Regs.DBFED = 10;
EPwm2Regs.DBRED = 10;
EPwm2Regs.ETSEL.bit.SOCAEN = 0;
EPwm2Regs.ETSEL.bit.SOCBEN = 0;
EPwm2Regs.ETSEL.bit.INTEN = 1;
EPwm2Regs.ETSEL.bit.INTSEL = 1;
EPwm2Regs.ETPS.bit.INTPRD = 1;
EPwm3Regs.TBPRD = 6250;
EPwm3Regs.TBCTR = 0x0000;
EPwm3Regs.TBCTL.bit.CTRMODE = 2;
EPwm3Regs.TBCTL.bit.SYNCOSEL = 3;
EPwm3Regs.TBCTL.bit.PHSDIR = 0;
EPwm3Regs.TBCTL.bit.PHSEN = 0;
EPwm3Regs.TBCTL.bit.CLKDIV = 0;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm3Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm3Regs.CMPCTL.bit.LOADBMODE = 0;
EPwm3Regs.CMPA.half.CMPA = 0;
EPwm3Regs.CMPB = 0;
EPwm3Regs.AQCTLA.all = 144;
EPwm3Regs.AQCTLB.all = 1536;
EPwm3Regs.AQCSFRC.bit.CSFA = 0;
EPwm3Regs.AQCSFRC.bit.CSFB = 0;
EPwm3Regs.AQSFRC.bit.RLDCSF = 0;
EPwm3Regs.DBCTL.bit.OUT_MODE = 3;
EPwm3Regs.DBCTL.bit.IN_MODE = 0;
EPwm3Regs.DBCTL.bit.POLSEL = 2;
EPwm3Regs.DBFED = 10;
EPwm3Regs.DBRED = 10;
EPwm3Regs.ETSEL.bit.SOCAEN = 0;
EPwm3Regs.ETSEL.bit.SOCBEN = 0;
EPwm3Regs.ETSEL.bit.INTEN = 1;
EPwm3Regs.ETSEL.bit.INTSEL = 1;
EPwm3Regs.ETPS.bit.INTPRD = 1;
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Start all the timers synced
EDIS;
}
In DefaultIsr.c file:
interrupt void EPWM1_INT_ISR(void)
{
}
Also I copied
EPwm1Regs.ETCLR.bit.INT = 1; PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
to DefaultIsr file but it didn't work.
Regards,
Pouriya