CCS/TMS320F28377S: Conflict between SPI and SCI

Tool/software: Code Composer Studio

I write two function to use UART and SPI port. When they called in main function the data on UART is corrupted otherwise they work fine(if I use any one at a time).

I use GPIO89, GPIO90 for UART and GPIO 58, GPIO60 for SPI.

So please help me to find out what is wrong??

/********************************************************************************SCI******************************************************************************************/

void init_serial_c(void)

{

GPIO_SetupPinMux(89, GPIO_MUX_CPU1, 6);
GPIO_SetupPinOptions(89, GPIO_OUTPUT, GPIO_ASYNC);

GPIO_SetupPinMux(90, GPIO_MUX_CPU1, 6);
GPIO_SetupPinOptions(90, GPIO_INPUT, GPIO_PUSHPULL);

EALLOW; // This is needed to write to EALLOW protected registers

PieVectTable.SCIC_RX_INT = &sciaRxFifoIsr;
// PieVectTable.SCIC_TX_INT = &scicTxFifoIsr;
EDIS; // This is needed to disable write to EALLOW protected registers

init_scic_gpio();
EALLOW;

PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER8.bit.INTx5 = 1; // PIE Group 9, INT1 rx interrupt enable
//PieCtrlRegs.PIEIER8.bit.INTx6 = 1; // PIE Group 9, INT2 tx interrupt enable

scic_echoback_init();
scic_fifo_init();

IER |= M_INT8;
//IER = 0x100; // Enable CPU INT
//EINT;
EINT;
ERTM;
EDIS;
}

/******************************************************************************************************************************************************/ 

void spi_fifo_init_net(void)
{
GPIO_SetupPinMux(2, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(2, GPIO_OUTPUT, GPIO_PUSHPULL); //cs1

GPIO_SetupPinMux(3, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(3, GPIO_OUTPUT, GPIO_PUSHPULL); //cs2

GPIO_SetupPinMux(10, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(10, GPIO_OUTPUT, GPIO_PUSHPULL); //E

GPIO_SetupPinMux(2, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(2, GPIO_OUTPUT, GPIO_PUSHPULL); //cs1

EALLOW;

GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO16 (SPISIMOA)
GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0; // Enable pull-up on GPIO18 (SPICLKA)

GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO16 (SPISIMOA)
GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // Asynch input GPIO18 (SPICLKA)

GpioCtrlRegs.GPBGMUX2.bit.GPIO58 = 3; // Configure GPIO16 as SPISIMOA
GpioCtrlRegs.GPBGMUX2.bit.GPIO60 = 3; // Configure GPIO18 as SPICLKA
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // Configure GPIO16 as SPISIMOA
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // Configure GPIO18 as SPICLKA

SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1;
SpiaRegs.SPIFFTX.bit.SPIFFENA = 1;
SpiaRegs.SPIFFTX.bit.TXFIFO = 0; //reset fifo pointer
SpiaRegs.SPIFFTX.bit.TXFIFO = 1;
SpiaRegs.SPIFFTX.bit.TXFFIENA = 1;
SpiaRegs.SPIFFTX.bit.TXFFIL = 0;

SpiaRegs.SPIFFTX.bit.TXFIFO=1;
SpiaRegs.SPIFFRX.bit.RXFIFORESET=1;

// Set reset low before configuration changes
// Clock polarity (0 == rising, 1 == falling)
// 16-bit character
// Enable loop-back --DISABLE LOOP BACK MODE

SpiaRegs.SPICCR.bit.SPISWRESET = 0;
SpiaRegs.SPICCR.bit.CLKPOLARITY = 1;
SpiaRegs.SPICTL.bit.CLK_PHASE = 0; //RISING EDGE WITH DELAY
SpiaRegs.SPICCR.bit.SPICHAR = (8-1); //(12-1); //7
SpiaRegs.SPICCR.bit.SPILBK = 0;

// Enable master (0 == slave, 1 == master)
// Enable transmission (Talk)
// Clock phase (0 == normal, 1 == delayed)
// SPI interrupts are enabled

SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
SpiaRegs.SPICTL.bit.TALK = 1;
SpiaRegs.SPICTL.bit.CLK_PHASE = 0;
SpiaRegs.SPICTL.bit.SPIINTENA = 1;

// Set the baud rate
ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 0x04; //7
SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 75; //125

SpiaRegs.SPIPRI.bit.FREE = 0;

//CLKCFGRegs.LOSPCP.bit.LSPCLKDIV=0x03;
// Release the SPI from reset

SpiaRegs.SPICCR.bit.SPISWRESET = 1;

//PieCtrlRegs.PIEIER6.bit.INTx2 = 1; // Enable PIE Group 6, INT 2
//IER=M_INT6; // Enable CPU INT6
//PieVectTable.SPIA_TX_INT = &spiAint;
// EDIS;

return;
}