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TMS320F28035: IO pins state during reset

Howard Zou
Genius 12365 points
Part Number: TMS320F28035


Hi,

I want to confirm that my understanding about the IO pin state during reset is correct.

1. warm reset is all kinds of reset except for POR reset, right?

2. BOOT-MODE pins refer to boot mode select pins(GPIO34,37) and the pins used during boot loading. If the boot mode is SCI boot mode, the BOOT-MODE pins will include the RX and TX pins for code transfer, right?

3. "x" lines refer to that the state of INTOSC1, X1/X2  and IO pins are unknown?

4. during reset(XRS/ held low) the GPIO pins are as input(state depends on internal PU/PD), it can be found in the manual that 

"The internal pullups on the pins that can be configured as ePWM outputs(GPIO0-
GPIO11) are all disabled asynchronously when the external reset signal (XRS) is low. The internal pullups
on all other pins are enabled on reset."

this is to prevent the PWM pins be high at the same time, right? But I'm confused that since it's input, why pull up circuit can still influence the voltage level on the pin? Can anyone tell me the difference when a GPIO is configured as an output or an input, at the circuit level?

5. BOR reset is not available in F2837x, F2807x and F28004x, so why don't we integrate BOR reset in the newer devices?

Figure 5-6 power-on reset

  • 0
    TI__Genius 17370 points
    Hello,
    I am writing to let you know that a C2000 team member has been assigned to this post and should be answering shortly.

    Regards
    Baskaran
  • 0
    TI__Guru* 95315 points

    1. Warm reset is all kinds of reset except for POR reset, right?

    Answer--> Correct.

     

    2. BOOT-MODE pins refer to boot mode select pins (GPIO34,37) and the pins used during boot loading. If the boot mode is SCI boot mode, the BOOT-MODE pins will include the RX and TX pins for code transfer, right?

    Answer--> In the general sense, BOOT-MODE pins refer to boot-mode-select pins. Note that in recent devices like F2837x, the boot-mode-select pins themselves are configurable. As also the peripheral-boot-pins for some peripherals like SCI, CAN, I2C and SPI. Perhaps we could use the terms boot-mode-select pins and peripheral-boot-pins to clearly distinguish what we are talking about.

     

    3. "x" lines refer to that the state of INTOSC1, X1/X2 and IO pins are unknown?

    Answer--> Correct.

     

    4. During reset (XRS/ held low) the GPIO pins are as input (state depends on internal PU/PD), it can be found in the manual that "The internal pullups .........are enabled on reset."

     

    This is to prevent the PWM pins be high at the same time, right? But I'm confused that since it's input, why pull up circuit can still influence the voltage level on the pin? Can anyone tell me the difference when a GPIO is configured as an output or an input, at the circuit level?

    Answer--> The pull-downs are turned off to prevent the possibility of turning on the gate drivers (by virtue of the pin being in a logic high state). Boards typically have an external pull-down resistor to prevent this scenario.

     

    5. BOR reset is not available in F2837x, F2807x and F28004x, so why don't we integrate BOR reset in the newer devices?

    Answer--> The device is specified to operate between MIN and MAX voltages specified in the datasheet. The device reliability is compromised outside of this range, where the BOR circuitry is active. This is the reason for the recommendation for an external BOR circuit.

  • 0 in reply to Hareesh Janakiraman
    TI__Genius 12365 points
    Hareesh,
    So you mean that the BOR is still available in F2837x, F2807x and F28004x, it's just the trip level is too low, right?
    If that's the case, I suggest that BOR should be added to the datasheet since right now it seems BOR is not available from the datasheet.
    Besides, what's the trip level of BOR for these devices?
    And what's the trip level for power on reset?

    Howard