TMS320F28377S: SPIRXINT Not Working SPI Slave, High Speed Clock

Hi all,

I am trying to use the SPIA peripheral as a slave along with the FIFO, in order to communicate with an FPGA at high speed.  I have the microcontroller setup to trip the SPIRXINT after 3, 8 bit words are received.  From the debugger I can see the RXFFINT bit is true, but I also see that the FIFO has completed filled and my ISR has not run.  The end result is that I can never service the SPI peripheral.  Any ideas as to why this isn't working. I've attached my configuration code and my routine that services the SPI module below.

void SPI_CNF(void){
    //Set SYSCLK divider ratio to 1 => 200MHz LSPCLK setting for SPI peripheral
    EALLOW;
    ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 0;
    EDIS;

	//SPICCR Registers
	SpiaRegs.SPICCR.bit.SPISWRESET = 0;
	SpiaRegs.SPICCR.bit.SPICHAR = 0x7;  //8-bit characters
	SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;  //Clock polarity (data out on rising clock edge)

	//SPICTL Reigsters
	SpiaRegs.SPICTL.bit.MASTER_SLAVE = 0;	//Configure as a slave to transmit on SPISOMIA
	SpiaRegs.SPICTL.bit.CLK_PHASE = 1;	//Clock phase, half cycle offset
	SpiaRegs.SPICTL.bit.TALK = 1;	//Enable data transmit via SPI
	SpiaRegs.SPICTL.bit.SPIINTENA = 1; 	//Enable SPI interrupts

	//SPIPRI Registers
	SpiaRegs.SPIPRI.bit.STEINV = 0;		//SPISTE bar acitve low
	SpiaRegs.SPIPRI.bit.TRIWIRE = 0;	//Normal 4 wire operation

	//SPICCR Register to enable high speed mode (50MHz max clock)
	SpiaRegs.SPICCR.bit.HS_MODE = 1;

	//SPIFFTX Registers
	SpiaRegs.SPIFFTX.bit.SPIFFENA = 1;  //Enable FIFO functionality

	//SPIFFRX Registers
	SpiaRegs.SPIFFRX.bit.RXFFIENA = 1;      //Enable FIFO RX interrupts
	SpiaRegs.SPIFFRX.bit.RXFFIL = 0x3;      //3 words received before interrupt is generated


	//SPIBRR Registers
	SpiaRegs.SPIBRR.all = 0;	//Set Baud rate to max rate

	SpiaRegs.SPIFFTX.bit.SPIRST = 1;
	SpiaRegs.SPIFFTX.bit.TXFIFO = 1;
	SpiaRegs.SPIFFRX.bit.RXFIFORESET = 1;   //Enable FIFO functionality
	SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1;
	SpiaRegs.SPICCR.bit.SPISWRESET = 1;
}

interrupt void spi_commuincation_isr(void){
    static command command_state;
    volatile int data_rx[3];
    volatile int data_tx[3];
    unsigned int i;

    for(i = 0; i < 3; i++){
        data_rx[i] = SpiaRegs.SPIRXBUF;
    }

    command_state = (command)data_rx[0];
    switch(command_state){
        case(FW_REVISION):  //Write FW Revision into TX FIFO
            data_tx[0] = g_status_word_fpga;
            data_tx[1] = (g_fw_revision | 0xFF00) >> 8;
            data_tx[2] = (g_fw_revision | 0x00FF);
            for(i = 0; i < 3; i++) {
                SpiaRegs.SPITXBUF=data_tx[i];
            }
            break;
        case(CONVERTER_INDEX):  //Read the converter index i.e. master, slave1, slave2, etc.
            data_tx[0] = g_status_word_fpga;
            data_tx[1] = 0;
            data_tx[2] = 0;
            g_converter_index = ((data_rx[1] << 8) + data_rx[2]);
            for(i = 0; i < 3; i++) {
                SpiaRegs.SPITXBUF=data_tx[i];
            }
            break;
        case(LOOP_BACK_MODE):   //Put most recently read data into TX FIFO
            data_tx[0] = g_status_word_fpga;
            data_tx[1] = data_rx[1];
            data_tx[2] = data_rx[2];
            for(i = 0; i < 3; i++) {
                SpiaRegs.SPITXBUF=data_tx[i];
            }
            break;
        default:
            data_tx[0] = g_status_word_fpga;
            data_tx[1] = 0xFFFF;
            data_tx[2] = 0xFFFF;
            for(i = 0; i < 3; i++) {
                SpiaRegs.SPITXBUF=data_tx[i];
            }
    }

    CPU2CLA_comm_fault = FALSE;

    SpiaRegs.SPIFFRX.bit.RXFFOVFCLR=1;  // Clear Overflow flag
    SpiaRegs.SPIFFRX.bit.RXFFINTCLR=1;  // Clear Interrupt flag
    PieCtrlRegs.PIEACK.all = M_INT6;

}

Best regards,

Lance Hummel