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TMS320F28375D: Addressing databus

EEngineer505
Prodigy 590 points
Part Number: TMS320F28375D


Hello,

I’ve got about the emif being set to 16-bit databus mode instead of 32-bit mode.  For the 16-bit mode if I write to a 16-bit word at an address offset in say chip select 4 such as 0x2000 – then on the physical emif address lines of the Delfino I am expecting to see 0x2000.

 

And if I write to address offset 0x2001 I will also see 0x2001 on the emif address pins of the Delfino.  Am I correct in my assumption?

 

Additionally, I have the Delfino connected to an fpga.  I’ve connected the full 32-bit databus of the emif and the 19-bit emif address bus of the Delfino to the fpga.  In 16-bit mode, when I do a write of a register (16-bit) in the fpga over the emif will the emif databus bits[31:16] be equal to 0’s?  And when I do a read of the same register in the fpga, is it okay to drive the same bits[31:16] with 0’s and have the 16-bit data be driven on bits[15:0]?

  • 0
    TI__Guru** 115611 points

    Hi,

    EMIF address bus (A[x:0]) is 32bit aligned. For 16bit mode, BA1 acts as LSB of address hence you will see correct address on A[x:0, BA1].

    Please refer "Figure 25-9. EMIF to 8-bit/16-bit Memory Interface" of device TRM.

    Additionally, I have the Delfino connected to an fpga.  I’ve connected the full 32-bit databus of the emif and the 19-bit emif address bus of the Delfino to the fpga.  In 16-bit mode, when I do a write of a register (16-bit) in the fpga over the emif will the emif databus bits[31:16] be equal to 0’s? 

    Value on data bus [31:16] does not matter because byte enables will not be active for upper 16bits. You need to connect the byte enables correctly.

    And when I do a read of the same register in the fpga, is it okay to drive the same bits[31:16] with 0’s and have the 16-bit data be driven on bits[15:0]?

    Again, value on data bus [31:16] does not matter. EMIF will ignore that value because it's 16bit READ hence you don't have to force 0x0 on [31:16].

    Regards,

    Vivek Singh

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Guru** 115611 points
    I hope this is clear. Let us know if you have any further queries.

    Vivek Singh
  • 0 in reply to Vivek Singh
    TI__Prodigy 590 points
    Hi Vivek,

    Thank you for your replies regarding the 16-bit mode of the emif. Another question I have for the 16-bit mode is that the byte strobes DQM0 and DQM1 are multiplexed with emif_addr[15] and emif_addr[16] respectively.

    Is there something that needs to be done in the DSP software (some initialization of the X-Bar) to have these byte strobes appear on these emif address pins or do they appear automatically when the chip select config register Asize is set to 16-bit mode. Besides setting the chip select config register do we have to do anything else to get the emif in 16-bit mode?
  • 0 in reply to EEngineer505
    TI__Guru 62975 points
    EE505,

    For 16-bit asynchronous mode, both Low and High bytes are always enabled because the C28x is 16-bit addressable.

    The A[16:15] and DQM[1:0] PinMux selections are mutually exclusive so you have the choice of either using the pins as DQM[1:0] where they are both enabled for every access, or you can use the pins as A[16:15] and statically tie the DQM pins of the FPGA enabled.

    -Tommy
  • 0 in reply to tlee
    TI__Prodigy 590 points

    For an asynch read on CS4,  I see the timing diagram below.  Does this imply that the DSP always expect the read data to be valid 2 clk cycles after the EM1OE_n goes active low?  Does this hold always – even if the DSP software specifies the strobe time to be a value of 10?

     

     

  • 0 in reply to EEngineer505
    TI__Guru 62975 points
    The number below the Setup, Strobe, and Hold text indicates the times configured through software.

    So in the example that you pasted:

    Setup = 2 EM1CLK cycles (R_SETUP = 1)
    Strobe = 3 EM1CLK cycles (R_STROBE = 2 )
    Hold = 2 EM1CLK cycles (R_HOLD = 1)
  • 0 in reply to tlee
    TI__Prodigy 590 points

    Our DSP software has the following settings for both async read and write:
    (0/8/1). ->
    Setup time = 1 emif clk
    Strobe time = 9 emif clks
    Hold time = 2 emif clks

    Then, per figure 25-11 is the Delfino expecting the data to be valid on the third clk cycle of the strobe period?
    Or is it expecting the read data to be valid on the 8th clock cycle of the strobe duration just before the EM1OE_n goes inactive?

    And am I correct in assuming that for our settings I don’t have to use the emif wait signal, em1wait? Can I just extend the strobe time to allow for any delay that the peripheral chip will have in driving the read data on the emif databus?


    FUNCTION PROTOTYPE TO UNDERSTAND THE PARAMETERS

  • 0 in reply to EEngineer505
    TI__Guru** 115611 points

    Hi,

    The number of cycles for each setting is configuration value + 1. If you have configured 2 for hold value then it'll be 3 cycle. Minimum hold is 1 cycle (programmed value 0) which is independent of strobe value.

    And am I correct in assuming that for our settings I don’t have to use the emif wait signal, em1wait? Can I just extend the strobe time to allow for any delay that the peripheral chip will have in driving the read data on the emif databus?

    You are right. Wait signal should be used if sometime data is available early and some time late. If it is fix delay then increasing the strobe value is good.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Prodigy 590 points

    I think there’s a misunderstanding in what I’m asking.  I understand about the +1 in the config reg.

     

    The item I’m not sure about is if the Delfino is expecting the read data to be valid 3 emif clock cycles after the falling edge of the em1oe_n signal. 

  • 0 in reply to EEngineer505
    TI__Guru 62975 points
    EM1OE will transition at the start of the STROBE stage. EMIF will read the EM1D bus at R_STROBE+1 cycles after the start of the STROBE stage.

    So I suppose you could say that Delfino is expecting the read data to be valid R_STROBE+1 cycles after the falling edge of the EM1OE signal.

    Don't forget to factor in the setup and hold timings from the datasheets.
  • 0 in reply to tlee
    TI__Guru** 115611 points
    This is getting discussed offline.