TMS320F28375D: Addressing databus

I hope this is clear. Let us know if you have any further queries.

Vivek Singh

Hi Vivek,

Thank you for your replies regarding the 16-bit mode of the emif. Another question I have for the 16-bit mode is that the byte strobes DQM0 and DQM1 are multiplexed with emif_addr[15] and emif_addr[16] respectively.

Is there something that needs to be done in the DSP software (some initialization of the X-Bar) to have these byte strobes appear on these emif address pins or do they appear automatically when the chip select config register Asize is set to 16-bit mode. Besides setting the chip select config register do we have to do anything else to get the emif in 16-bit mode?

EE505,

For 16-bit asynchronous mode, both Low and High bytes are always enabled because the C28x is 16-bit addressable.

The A[16:15] and DQM[1:0] PinMux selections are mutually exclusive so you have the choice of either using the pins as DQM[1:0] where they are both enabled for every access, or you can use the pins as A[16:15] and statically tie the DQM pins of the FPGA enabled.

-Tommy

For an asynch read on CS4,  I see the timing diagram below.  Does this imply that the DSP always expect the read data to be valid 2 clk cycles after the EM1OE_n goes active low?  Does this hold always – even if the DSP software specifies the strobe time to be a value of 10?

 

 

The number below the Setup, Strobe, and Hold text indicates the times configured through software.

So in the example that you pasted:

Setup = 2 EM1CLK cycles (R_SETUP = 1)
Strobe = 3 EM1CLK cycles (R_STROBE = 2 )
Hold = 2 EM1CLK cycles (R_HOLD = 1)

Our DSP software has the following settings for both async read and write:
(0/8/1). ->
Setup time = 1 emif clk
Strobe time = 9 emif clks
Hold time = 2 emif clks

Then, per figure 25-11 is the Delfino expecting the data to be valid on the third clk cycle of the strobe period?
Or is it expecting the read data to be valid on the 8th clock cycle of the strobe duration just before the EM1OE_n goes inactive?

And am I correct in assuming that for our settings I don’t have to use the emif wait signal, em1wait? Can I just extend the strobe time to allow for any delay that the peripheral chip will have in driving the read data on the emif databus?

FUNCTION PROTOTYPE TO UNDERSTAND THE PARAMETERS

Hi,

The number of cycles for each setting is configuration value + 1. If you have configured 2 for hold value then it'll be 3 cycle. Minimum hold is 1 cycle (programmed value 0) which is independent of strobe value.

And am I correct in assuming that for our settings I don’t have to use the emif wait signal, em1wait? Can I just extend the strobe time to allow for any delay that the peripheral chip will have in driving the read data on the emif databus?

You are right. Wait signal should be used if sometime data is available early and some time late. If it is fix delay then increasing the strobe value is good.

Regards,

Vivek Singh

I think there’s a misunderstanding in what I’m asking.  I understand about the +1 in the config reg.

 

The item I’m not sure about is if the Delfino is expecting the read data to be valid 3 emif clock cycles after the falling edge of the em1oe_n signal. 

EM1OE will transition at the start of the STROBE stage. EMIF will read the EM1D bus at R_STROBE+1 cycles after the start of the STROBE stage.

So I suppose you could say that Delfino is expecting the read data to be valid R_STROBE+1 cycles after the falling edge of the EM1OE signal.

Don't forget to factor in the setup and hold timings from the datasheets.

This is getting discussed offline.