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TMS320F28377D: TMS320F28377D CLA_task & XINT4 trigger

Part Number: TMS320F28377D


Dear readers,

Configuration:

I've a CLA task triggered by the XINT4 logic.                               (CLA interrupt 32 on task 7)

The XINT4 logic as falling edge and enabled, corresponding inbar is set to GPIO66 (as input and qualifier enabled).

Usage:

When triggered (used as chip select) the task waits for data from a master and proccess (CRC)..

Problem:

The CLA triggers on falling edge, with external reference of 10KHz, and task starts and waits for the data to receive, that works just fine.

Problem is that is seems that the task is triggered by the previous interrupt event, the interrupt overflow flag is set for the task.

Question:

When CLA task is triggered,when is the task clearing the event? At task start, or at task end?

Is it possible to clear the interrupt in CLA code (like a PIEACK)?

Best regards

  • Hi Tjarco,

    The RUN bit and the CLA Task even will be cleared when that Task executes an MSTOP. Therefore, the task will be cleared at the end of the task upon completion.

    It will automatically clear the task bit.

    It sounds like your task is not completing in time before the task is triggered again.

    FYI, the CLA is a floating point engine and may not perform a CRC most efficiently. The F2837xD C28x CPU has a VCU engine which performs CRC very efficiently. It will likely be faster to perform the CRC on the C28x and assign some other task to the CLA.

    sal
  • Thank you for your reply.

    That' wont be an option, the CPU1 core is also time critical (high speeds SCI) and the CLA1 does not share memory directly with CPU2 or CLA2.

    So i'm stuck with this configuration.

    I introduced an "sync" and the Overflow is gone now,

  • Very good. Glad you got your control flow working properly.

    sal