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TMS320F28379D: Memory and BIST Question

Chuchen Wang
Expert 3470 points
Part Number: TMS320F28379D


Hi,

My customer has a couple of questions on C2000 below:

1) Can CPU 2 flash be accessed from CPU 1?

Looks like one CPU cannon access the second core's flash as TRM suggests they are dedicated flash regions.  But the system does have a global shared RAM memory section and MSG RAMs used to interchange data between CPU cores, and a CPU core and CLA1.  Please confirm.

2) What does the hardware BIST test for?  Do we have material we can share?

Thanks,

Chuchen

  • 0
    TI__Guru** 115881 points

    Hi Wang,

    1) CPU 2 flash be accessed from CPU 1?

    No, flash are dedicated memory for each CPU.

    Looks like one CPU cannon access the second core's flash as TRM suggests they are dedicated flash regions.  But the system does have a global shared RAM memory section and MSG RAMs used to interchange data between CPU cores, and a CPU core and CLA1.  Please confirm.

    Your understanding is correct. GSxRAM are shared RAM between two CPU and LSxRAM are shared RAM between CPU and it's CLA. In addition it has MSGRAMs to exchange the info.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Guru** 115881 points

    About hardware BIST, it's for testing the CPU logic. We will have other expert to provide detail about this.

    Regards,

    Vivek Singh