TMS320F28377S: HRPWM in UpDown mode without Auto Conversion

Part Number: TMS320F28377S

Hello,

I have a few questions about the HRPWM in UpDown mode without Auto Conversion.

Is it possible to create a symmetric HRPWM in this mode? If yes, which EDGMODE do i have to use?

At the moment I compare one HR PWM (EPWM2A) and one ePWM (EPWM2B). They both use the same CMP value (CMPA=CMPB) and i only change the CMPAHR value(by changing currentSample).

If I use BEP, the HIGH pulse is only shifted and not increased or decreased in comparison to the ePWM.

If I use MEP and a MEP_ScaleFactor of 120, i can increase or decrease the duty cycle, but it seem, that it is not longer symmetric to PRD.

I guess for using FEP it would be the same, but for that i would had to Change the logic.

In Auto Conversion mode a similiar Project is running, so i think the Overall Settings are okay. 

My Code:

 InitEPwm();

    // Mapping Interrupts
    EALLOW;
    PieVectTable.EPWM2_INT = &epwm_isr;
    EDIS;

//Main program loop - continually sample temperature
    for(;;)
    {
        if(isr_flag==1)
        {

            //Sample ADCIN14
            // Mit der Funktion und forcen
            //GpioDataRegs.GPBTOGGLE.bit.GPIO42 = 1; // Anzeigen dass gelesen wird
            currentSample = sampleADC();
            //GpioDataRegs.GPBTOGGLE.bit.GPIO42 = 1; // Anzeigen dass gelesen wurde
            // Alternative mit getriggerter PWM
            // da 12 bit Auflösung max 4096
            Q_duty_cycle=32768-8*currentSample; // da cS max 4096 (0%-100% in Q15)
            // cmpa_value bestimmen
            cmpa_value=(Q_duty_cycle*counter_max)>>15;
            // Differenz in Q15
            Q_fraction=(Q_duty_cycle*counter_max)-(cmpa_value<<15);
            cmpahr_value=((Q_fraction*MEP_ScaleFactor)+(0x0080<<7))>>15;
            cmpahr_value=cmpahr_value<<8;

            EPwm2Regs.CMPA.bit.CMPA = cmpa_value;
            EPwm2Regs.CMPB.bit.CMPB = cmpa_value;
            EPwm2Regs.CMPA.bit.CMPAHR= cmpahr_value;


            isr_flag=0;

        }
}

void InitEPwm()
{
    // PWM1 wird nicht herrausgeführt -> EPWM2

    // Enable PWM Clock
    CpuSysRegs.PCLKCR2.bit.EPWM2=1;

    // evtl Enable HRPWM Clock
    CpuSysRegs.PCLKCR0.bit.HRPWM=1;

    // Reset EPWMCLK=SYSCLK/2
    EALLOW;
    ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=1;
    EDIS;

    // Init GPIO Settings
    InitEPwm2Gpio();

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
    EDIS;

    // Setup TBCLK
    EPwm2Regs.TBPRD = counter_max;           // Set Maximum Value for Up/Down Counting
    EPwm2Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
    EPwm2Regs.TBCTR = 0x0000;                  // Clear counter

    // Set Compare values
    EPwm2Regs.CMPA.bit.CMPA = cmpa_value;    // Set compare A value
    EPwm2Regs.CMPA.bit.CMPAHR=(0<<8);
    EPwm2Regs.CMPB.bit.CMPB = cmpb_value;    // Set Compare B value

    // Setup counter mode
    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down                           //
    //EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;     // Count up
    EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;        //  Enable laden der Phase in den Counter bei Synchronisation
                                                  // bei Counter up down (+ HR ) notwendig
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;          

    EPwm2Regs.TBCTL.bit.SYNCOSEL   = TB_SYNC_DISABLE; 

    // Setup shadowing
    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    // Set actions
    // Up down
    EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;            // Set PWM1A on event A, up
                                                  // count
    EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;          // Clear PWM1A on event A,
                                                  // down count

    EPwm2Regs.AQCTLB.bit.CBU = AQ_SET;            // Set PWM1B on event B, up
                                                  // count
    EPwm2Regs.AQCTLB.bit.CBD = AQ_CLEAR;          // Clear PWM1B on event B,
                                                  // down count

    // Interrupt where we will change the Compare Values
    EPwm2Regs.ETSEL.bit.INTSEL = 3;     // Select INT on: 1 = Zero  2 = max 3 = zero+max
    EPwm2Regs.ETSEL.bit.INTEN = 1;                // Enable INT
    EPwm2Regs.ETPS.bit.INTPRD = ET_1ST;           // Generate INT on 1st (3rd) event

    // HR Einstellungen
    EALLOW;
    EPwm2Regs.HRCNFG.all =0x0;
    EPwm2Regs.HRCNFG.bit.HRLOAD=2;          
    EPwm2Regs.HRCNFG.bit.AUTOCONV=0;
    EPwm2Regs.HRCNFG.bit.EDGMODE=1;         
    EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP;   


    EDIS;

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;



    EDIS;
}


//
__interrupt void epwm_isr(void)
{
    isr_flag=1;
    // Clear INT flag for this timer
    EPwm2Regs.ETCLR.bit.INT = 1;

    // Acknowledge this interrupt to receive more interrupts from group 3
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}