TMS320F28335: TMS320F28335

Lei,

Does external ref clock mean the main input clock for the device (like crystal on X1 and digital clock on XCLKIN)?

Can you describe how you would like the ADC to be synchronized?

The ADC is usually synchronized with the EPWMs on the device. Is that an option?

Triggering with an external signal is possible with XINT2 from GPIO0-31.

-Tommy

HI Tommy
Ths.
Does external ref clock mean the main input clock for the device (like crystal on X1 and digital clock on XCLKIN)? yes. now 30M


The ADC is usually synchronized with the EPWMs on the device. Is that an option? yes,by the EPWMS

Triggering with an external signal is possible with XINT2 from GPIO0-31. Yes. I do it

Can you describe how you would like the ADC to be synchronized?
the ADC Internal clock if from external clock by the pLL and frequency doubling in chips. But when the external clock is rising or falling, the ADC clock is not rising or falling. Can do it or other way? just like when external clock rising or falling the adc clock instant-on by clearing

Lei,

I think it will be difficult to synchronize the ADC directly with the X1/CLKIN clock signal when the PLL is enabled. The PLL is designed to multiply frequencies with no guarantee as to the phase relationship between the input and output clocks.  Bypassing the PLL might work, but your operating frequency will obviously be much slower.

If you are trying to share a common clock with external circuitry for synchronization, it would be easier to generate the clock output signal using an EPWM output -- then the ADC will be coherent.

-Tommy