TMS320F28379D: EMIF Interface to two 512Mbits SDRAM chips

That was of absolutely no help, was it? Sorry about that, I have been focused on a different EMIF problem and didn't bother to look.

Okay, so yes, it does support 32 bits.

The diagram you found is close, but you don't need to pull up CKE and the address lines are more straightforward with the EMIF on the Delfino.

The EMIF has its own Bank Address bits. There is a chart/table on page 2417 (Table 25-15) for 16 bit parts (even if you are using two 16 bit parts, you still want to use this table). Use Table 25-15 in conjunction with Table 25-7 (page 2408) to select the number of address lines to use.

For example, I am correlating all this with a IS42S16400J from ISSI (www.issi.com/.../42-45S16400J.pdf), which is a 64Mx16x4Bank part.

I would connect (to both parts):
EM1CLK to CLK
EM1SDCKE to CKE
EM1RAS/CAS to RAS/CAS
EM1CS0 to CS
EM1WE to WE
EM1A0:11 to A0:11
EM1BA0:1 to BA0:1

These next set of pins (EM1DQM0:3) I could not find confirmation. If narrow mode is off (page 2409, table 25-8), I would suspect that EM1DQM2:3 pins control bytes 3 and 4 of the 32 bit word, but we should get confirmation from TI on this. Table 25-14 suggests the EM1DQM pins are used as part of the address for 32 bit parts. However, the 32 bit parts I looked at call for EM1DQM0:3 to be connected to DQM0:3. So I am not 100% sure what 25-14 is trying to say and gives me pause as to how the EM1DQM2:3 pins behave when EMIF is using a 32 bit data interface.

Putting my fear aside, and if my assumption is correct the following is needed
EM1DQM0:1 to the low part LDQM and UDQM (0 to LDQM, 1 to UDQM
EM1DQM2:3 to the upper part LDQM and UDQM (2 to LDQM, 3 to UDQM)

If the above is not correct, then that would probably affect how the data lines are connected to the high and low parts as the EM1DQM0:1 pins would be masking words instead of bytes? The EMIF section is eerily quiet about a 32 bit data interface....

For the data pins, 0:15 connect to the low DQ pins and 16:31 connect to the high DQ pins.

Well, hopefully this is more helpful than my first response. I think the only question that we need to answer here is how EM1DM2 and 3 are utilized with NM == 0.

Good luck :)

Kevin

EDIT:  I am starting to second guess myself on this.  25-14 is non-verbally suggesting the EMIF behaves differently when NM == 0.  There is no direct reference to 32 bit data interfaces and that has me concerned.  I can't seem to find the check box to uncheck this as a suggested answer.  We really need to hear from TI on this.