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TMS320F28069: ePWM Module Synchronization problem

Ramesh Palanisamy
Intellectual 620 points
Part Number: TMS320F28069

Hi TI experts,

I have a below requirement to synchronize the ePWMs for one of my application.I am using MCU - TMS320F28069.

ePWM 4 (master) // act as Sync down-stream module
ePWM 6 (slave) // act as sync flow-through module
ePWM 1 (slave) // act as sync flow-through module

The code segment for initialization is shown below.I just followed Time-Base Counter Synchronization
Scheme 1 as per application note for TMS320F28069 MCU.

void InitEPwm4(void)
{
    EALLOW;
               
               EPwm4Regs.TBPRD = 3600;                        // Set timer period
               EPwm4Regs.CMPA.half.CMPA =1800;
               EPwm4Regs.CMPB =400;
               EPwm4Regs.TBPHS.half.TBPHS = 0x0000;           // Phase is 0
               EPwm4Regs.TBCTR = 0x0000;                      // Clear counter
               EPwm4Regs.TBCTL.bit.PHSEN = 0 ;
               // Setup TBCLK
               EPwm4Regs.TBCTL.bit.CTRMODE = 0; // Count up

               EPwm4Regs.TBCTL.bit.PRDLD = 0;
               EPwm4Regs.TBCTL.bit.SYNCOSEL = 1;          // setup Sync down-stream module
               EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0;       // Clock ratio to SYSCLKOUT
               EPwm4Regs.TBCTL.bit.CLKDIV = 0;

               EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0;    // Load registers every ZERO
               EPwm4Regs.CMPCTL.bit.SHDWBMODE = 0;
               EPwm4Regs.CMPCTL.bit.LOADAMODE = 0;
               EPwm4Regs.CMPCTL.bit.LOADBMODE = 0;

               // Set actions
               EPwm4Regs.AQCTLA.bit.ZRO = 1; // set actions for EPWM1A
               EPwm4Regs.AQCTLA.bit.CAU = 2;

               EPwm4Regs.AQCTLB.bit.PRD = 1; // set actions for EPWM1B
               EPwm4Regs.AQCTLB.bit.CBD = 2;
        EDIS;
}

void InitEPwm6(void)
{
    EALLOW;
                        
               EPwm6Regs.TBPRD = 1800;                        // Set timer period
               EPwm6Regs.CMPA.half.CMPA =400;
               EPwm6Regs.CMPB =400;
               EPwm6Regs.TBPHS.half.TBPHS = 0x0000;           // Phase is 0
               EPwm6Regs.TBCTR = 0x0000;                      // Clear counter
               EPwm6Regs.TBCTL.bit.PHSEN = 1 ;
               // Setup TBCLK
               EPwm6Regs.TBCTL.bit.CTRMODE = 0; // Count up
               EPwm6Regs.TBCTL.bit.PRDLD = 0;
               EPwm6Regs.TBCTL.bit.SYNCOSEL = 0; // setup sync flow-through
               EPwm6Regs.TBCTL.bit.HSPCLKDIV = 0;       // Clock ratio to SYSCLKOUT
               EPwm6Regs.TBCTL.bit.CLKDIV = 0;

               EPwm6Regs.CMPCTL.bit.SHDWAMODE = 0;    // Load registers every ZERO
               EPwm6Regs.CMPCTL.bit.SHDWBMODE = 0;
               EPwm6Regs.CMPCTL.bit.LOADAMODE = 0;
               EPwm6Regs.CMPCTL.bit.LOADBMODE = 0;

               // Set actions
               EPwm6Regs.AQCTLA.bit.ZRO = 1; // set actions for EPWM1A
               EPwm6Regs.AQCTLA.bit.CAU = 2;

               EPwm6Regs.AQCTLB.bit.PRD = 1; // set actions for EPWM1B
               EPwm6Regs.AQCTLB.bit.CBD = 2;
    EDIS;
}

void InitEPwm1(void)
{
EALLOW;
    // Enter Period value
   EPwm1Regs.TBPRD = 1800;                        // Set timer period
   EPwm1Regs.CMPA.half.CMPA =400;
   EPwm1Regs.CMPB =400;
   EPwm1Regs.TBPHS.half.TBPHS = 0x0000;           // Phase is 0
   EPwm1Regs.TBCTR = 0x0000;                      // Clear counter
   EPwm1Regs.TBCTL.bit.PHSEN = 1 ;
   // Setup TBCLK
   EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Count up

   EPwm1Regs.TBCTL.bit.PRDLD = 0;
   EPwm1Regs.TBCTL.bit.SYNCOSEL = 0; // setup sync flow-through
   EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;       // Clock ratio to SYSCLKOUT
   EPwm1Regs.TBCTL.bit.CLKDIV = 0;

   EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;    // Load registers every ZERO
   EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
   EPwm1Regs.CMPCTL.bit.LOADAMODE = 0;
   EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;   

   // Set actions
   EPwm1Regs.AQCTLA.bit.ZRO = 1; // set actions for EPWM1A
   EPwm1Regs.AQCTLA.bit.CAU = 2;

   EPwm1Regs.AQCTLB.bit.PRD = 1; // set actions for EPWM1B
   EPwm1Regs.AQCTLB.bit.CBD = 2;
EDIS;
}
//*******************//

The ePWM modules 4 & 6 are perfectly synchronized with two different frequencies whereas 4 & 1 is not working.It is noticed that both PWMs are starting at the same edges.
But ePWM 1 module is not synchronised with ePWM 4.The PWM frequencies of modules ePWM6 & ePWM1 are same & different from ePWM4(master).

Is it due to the fact that the ePWM 1 module can not be set as sync flow-through
while ePWM 4 acts as Sync down-stream module as per above code ?
Pls suggest any corrections so as to sync ePWM 4 & ePWM 1 modules.

Thanks & regards,

Ramesh P



  • 0
    TI__Mastermind 42055 points

    Ramesh,

    it seems like you should swap the function of ePWM1 and ePWM4, this would allow you to sync everything to one PWM. Does this work for your application? 

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Intellectual 620 points
    Hi Cody,

    Thanks for your reply.

    Once again,i make clear about my requirement.
    //**************************************************//
    ePWM 4 must be Master whose frequency is 25 kHz.
    ePWM 1 must be Slave whose frequency is 50 kHz.
    //**************************************************//

    I should be able to adjust the phase shift of ePWM1 with respect to ePWM 4.

    I swapped the ePWM1 and ePWM4 as you suggested.But the frequency of both of them are still at 50 kHz.
    I understood the reason from the following post which is exactly discussing about my requirement.

    e2e.ti.com/.../264347

    Pls go through case 2 in the following reply.But still i am not getting right conclusion about this issue.
    How to get two different frequencies for ePWM 4 as master & ePWM 1 as slave (whose phase should be adjusted with respect to ePWM4)?


    //****************************************************************************************************//
    May 13, 2013 4:28 PM

    In reply to Brett Larimore:

    Hi Brett,

    One More concern.

    Is it necessary Slave should be operating higher OR equal frequency compare to frequency of Master PWM during synchronization.

    for example: ePWM2_(Master), ePWM3_(Slave) during PWM synchronization, Frequency of ePWM3 >= Frequency of ePWM2. If Yes then why?

    Best Regards,

    Prem


    May 13, 2013 4:13 PM

    In reply to prem shukla:

    Prem,

    Synchronization occurs when an upstream PWM reaches its ZRO event (or maybe CMPB).

    Let's assume that you're synchronizing PWM2 and PWM3 together.

    Case 1: If PWM2 runs at 50kHz and PWM3 runs at 100kHz, PWM2 will generate a synchronization event every 50kHz. PWM3 will finish 2 full periods before it gets the upstream synchronization event which forces it to a certain value. Everything should work nicely.

    Case 2: If you want PWM2 to run at 100kHz and PWM3 to run at 50kHz, PWM2 will generate a synchronization event every 100kHz. However, PWM3 will never finish a full period before the upstream synch event occurs which will force it back to a certain value. Because of this, PWM2 and PWM3 will effectively be 100kHz signals. Note that this really isn't an issue as long as you expect it.

    In most application cases, you'd want the frequency of PWM3 to be an integer multiple of PWM2. (as long as you understand what the module is doing, other ideas are possible though)

    Hopefully this answers your question. Let me know if it doesn't.

    Thank you,
    Brett

    //****************************************************************************************************//

    As my hardware has some limitation,i have to strictly follow the below condition.

    ePWM 1 must be a slave & i have to adjust the PHASE of ePWM1 with respect to ePWM4.
    ePWM 1 must follow ePWM4.For that,ePWM4 must be a MASTER & ePWM1 must be a slave.

    Hope the above information is clear to you & help me to get rid out of this issue.

    Regards,
    Ramesh P
  • 0 in reply to Ramesh Palanisamy
    TI__Mastermind 42055 points

    Ramesh,

    "
    Case 2: If you want PWM2 to run at 100kHz and PWM3 to run at 50kHz, PWM2 will generate a synchronization event every 100kHz.  However, PWM3 will never finish a full period before the upstream synch event occurs which will force it back to a certain value.  Because of this, PWM2 and PWM3 will effectively be 100kHz signals.  Note that this really isn't an issue as long as you expect it.

    "

    If your are in case 2 as described above, you have two options that I can think of:

    1. Make  PWM1 the 25KHz signal and PWM4 the 50KHz signal and use the ePWM normally. This will cause the slower signal to synchronize to the faster one and everything should work.
    2. Disable the periodic sync signals between PWM4 and PWM1 and attempt to use software sync's to update the period as needed for PWM1.(I expect that this would be difficult to do, but it could be possible depending on your code)

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Intellectual 620 points

    Cody,

    Thanks for your suggestion.

    Right now,i have managed the situation with ePWM8A by critically modifying the hardware .

    I will try the option 2 later & get back to you in case of any problem.

    regards,

    Ramesh P