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Compiler/TMS320F28054M: Issue with comparetor

Part Number: TMS320F28054M


Tool/software: TI C/C++ Compiler

I am trying to use compareter to detect motor short circuit protection. For this I activated all relevant functions in 

void HAL_setupAfe(HAL_Handle handle) function in Hal.c file. The comparetor is properly activated. I have enabled both output GPIO 15 to see trip status on CRO & actual trip taking all precautions as per data sheet. I also activated filter comparetor clocks.

Things are working fine, but I have two querries

1. To stop PWM, am I required to set any bits in trip zone register? If yes, which register?

2. If digital filter is activated then

In CTRIPM1STS register, which shows comparetor status, bits CTRIPOUTM1FLG(bit 15) and CTRIPA3FLG(bit 9) bits operate as expected, but

 CTRIPOUTMISTS(bit 7) and CTRIPA3STS(bit 1) keep fluctuating between 1 and 0 inside realtime watch window of CCS. & GPIO 15 configured as comparetor status shows high frequency square wave on out put when low and output as high when high (as expected)

however, if digital filter is not used by fluctuating stops.

In view of above, is there any initialization part which I might be missing?

  • The HAL_disablePwm() API call has the following TZ actions forced, which will stop PWM generation:
    EPWM_forceTripZoneEvent(obj->pwmHandle[0], EPWM_TZ_FORCE_EVENT_OST);
    EPWM_forceTripZoneEvent(obj->pwmHandle[1], EPWM_TZ_FORCE_EVENT_OST);
    EPWM_forceTripZoneEvent(obj->pwmHandle[2], EPWM_TZ_FORCE_EVENT_OST);

    I'm not sure about the second question, I will have another member of the team look into it

    Sean
  • Thanks I will try the same.

    One more point I realized for comparetor trip is that instead of showing high the GPIO output shows a square wave, whose frequency is exactly the sampling frequency of digital filter set by register CTRIPA3FILCLKCTL. If I change the the count in this register, the frequency coming out of GPIO pin changes in exact manner accordingly. Does that point to something?

  • My problem seems to have gone after setting CTRIPA1FILCTL register initial value (ie. bit 15) to 1. Can anybody pl. give me some explanation?

  • Milind,

    Maybe you had some noise that was being picked up? It is possible that you did not have the filtering setup correctly, the last step to setting up filtering is to enable bit 15 of CTRIPxxFILCTL.

    To ensure proper operation of the digital filter, the following initialization sequence is recommended:

    1. Configure and enable comparators for operation in CTRIPxxICTL
    2. Configure the digital filter parameters for operation
      1. Set CTRIPxxFILCTL_SAMPWIN for the number of samples to monitor in FIFO window
      2. Set CTRIPxxFILCTL_THRESH for the threshold required for majority qualification
      3. Set the digital filter clock prescale value in CTRIPxxFILCLKCTL to the desired value

    3. Initialize the sample values in the digital filter FIFO window by setting CTRIPxxFILCTL_FILINIT

    Regards,
    Cody