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CCS/TMS320F28377D: C28x Microcontrollers multi day workshop. Lab 9 CLA. CPU1 storing data calculated by the CLA?

Leonardo Callegaro
Expert 1605 points
Part Number: TMS320F28377D
Other Parts Discussed in Thread: CONTROLSUITE, C2000WARE

Tool/software: Code Composer Studio

Hi there,

I am trying to understand how the CLA operates, so I have followed the Lab 9 exercise, re: chapter 9 of "C2000 Microcontroller Workshop, rev 6.1, May 2015", Multi day Workshop. In the exercise a FIR filter calculation is executed by the CLA. What I would like to clarify is: how does the CPU "know" the filtered result of the calculation made by the CLA? Is this done by means of a CLA interrupt? Under what instruction?

Any simple explanation would help.

Thank you so much,

Best Regards

Leo

 

  • 0
    TI__Genius 17315 points

    Leo,       

    I will explain the lab exercise code flow from the beginning and hopefully this will answer your question.  After initialization is completed in main() the ‘while(1)’ loop is entered.  The ADC is triggered by ePWM2 at a rate of 50 kHz.  In Adc.c notice that the ADCA1INT1 interrupt has been commented out:

          // PieCtrlRegs.PIEIER1.bit.INTx1 = 1;

    This ISR was used in the previous lab exercised, but instead in this lab exercise the CLA Task1 ISR will be used.  In Cla.c now notice that ADCAINT1 is being used as a trigger source for CLA Task1.

          DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK1 = 1;   // 1=ADCAINT1

    Once the trigger is generated the CLA filter is run (either from ClaTasks.asm or ClaTasks_C.cla).  When the Task1 filter code completes execution, the CLA triggers the CPU ISR.  In Cla.c see the following code lines:

          PieCtrlRegs.PIEIER11.bit.INTx1 = 1; // Enable CLA Task1 in PIE group #11

          IER |= 0x0400;                                     // Enable INT11 in IER to enable PIE group 11

    At this point code execution continues in DefaultIsr.c at:

          interrupt void CLA1_1_ISR(void)   // PIE11.1 @ 0x000DE0 CLA1 interrupt #1

    After the ISR completes execution, the ‘while(1)’ loop in main.c is entered again and the process repeats.

    I hope this helps.

    - Ken

  • 0 in reply to Ken Schachter
    Expert 1605 points

    Hi Ken,

    Thank you so much for the comprehensive answer, it certainly helps.

    So, my understanding is that the key point here is that "when the Task1 filter code completes execution, the CLA triggers the CPU ISR". This is carried out thanks to the following setting in the file Cla.c:

     PieCtrlRegs.PIEIER11.bit.INTx1 = 1; // Enable CLA Task1 in PIE group #11

 IER |= 0x0400;                      // Enable INT11 in IER to enable PIE group 11

    In other words, the above code gives the instruction to generate a CPU1 Interrupt when the Task 1 in CLA1 has been completed, i.e. when the whole code inside Task 1 (of CLA1) has been executed.

    Now, inside DefaultIsr.c, within the "interrupt void CLA1_1_ISR(void)", I can see that the CLA filter result, ClaFilteredOutput, is passed to the CPU variable AdcBuf by means of:

    //--- Read the CLA filter result
*AdcBufFilteredPtr++ = ClaFilteredOutput;	// Read the CLA filter output

    so, I assume that at this stage since the CLA task1 has completed, the value of ClaFilteredOutput is known by the CPU1. Hopefully my understanding is correct.

    Thank you very much again,

    Leo

  • 0 in reply to Leonardo Callegaro
    TI__Genius 17315 points

    Leo,

    Yes, your understanding is correct.  When Task1 is completed, the CLA triggers the CPU ISR.  To prove this, simply comment out:

          // PieCtrlRegs.PIEIER11.bit.INTx1 = 1; // Enable CLA Task1 in PIE group #11

    and you will notice that the ISR will not execute.  This code line closes the PIE IER switch allowing the interrupt to propergate to the CPU core, assuming the other required switches are set correctly.  For reference, please see the lower slide on page 4-14 and the slide on page 4-18 in the workshop manual.

    Once the Task1 completes, execution flow continues in the ISR, where as you pointed out, the filter results are read from ClaFilteredOutput and placed in a circular buffer.  You will notice in main.c a data section is created (near the top) for 'ClaFilteredOutput' to pass the results to the CPU using the 'Cla1ToCpuMsgRAM'.  This section is assigned to a memory address in the Lab.cmd linker command file.

    I hope you found my workshop materials useful.

    - Ken

  • 0 in reply to Ken Schachter
    Expert 1605 points

    Hi Ken,

    Thank you once again for the comprehensive answer. It certainly helps. For reference, 

     PieCtrlRegs.PIEIER11.bit.INTx1 = 1; // Enable CLA Task1 in PIE group #11

    closes the PIEIER switch, as shown in 4-14 and 4-18, reported below.

    OK. I think I got another key point, that is as you have explained: the "ClaFilteredOutput" which is inside the CLA is passed to the CPU thanks to the command: 

    #pragma DATA_SECTION(ClaFilteredOutput, "Cla1ToCpuMsgRAM");

    defined at the top of Main_9.c, in the Lab9 project. I think that this is what I was looking for initially.

    Your workshop material is very useful. If there are other examples regarding the operation of the CLA  out there (the simpler the better) it would be great to know.

    Thank you again for your time,

    Best Regards

    Leo 

  • 0 in reply to Leonardo Callegaro
    TI__Genius 17315 points

    Leo,

    Thank you for your reply.  You can find some CLA code examples in controlSUITE / C2000Ware.  Also, I think you might find the following video series "Control Law Accelerator (CLA) Hands-On Workshop" to be interesting, and it can be found at:

    https://training.ti.com/control-law-accelerator-cla-hands-workshop

    - Ken