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Compiler/TMS320F28377D: Why the CLK of 28377d cannot exceed 30MHz ?

user5063758
Prodigy 230 points
Part Number: TMS320F28377D

Tool/software: TI C/C++ Compiler

I use the controlsuit example "blinky_cpu01" of 28377D .

when I config the sysclk ," InitSysPll(XTAL_OSC, IMULT_20, FMULT_0, PLLCLK_BY_2);"  The CCS will prompt error:

C28xx_CPU1: Error: (Error -1044 @ 0x0) The debug probe reported an error. Confirm debug probe configuration and connections, reset the debug probe, and retry the operation. (Emulation package 5.1.641.0)
C28xx_CPU1: Unable to determine target status after 20 attempts
C28xx_CPU1: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging

but when I config the sysclk ," InitSysPll(XTAL_OSC, IMULT_3, FMULT_0, PLLCLK_BY_2);"  It will generate 30MHz CLK, the program will run normally. and the LED will blinky slowly.

I want to know why I cannot config the CLK normally.

  • 0
    TI__Guru 62975 points
    Are you using a TI evaluation board or something else?
  • 0 in reply to tlee
    Prodigy 230 points
    I use the circuit boards that I designed with 28377D
  • 0 in reply to user5063758
    TI__Genius 15385 points

    Hi,

    It looks like current starvation issue, when you try to lock the PLL at 200MHz and use that as SYSCLK, there will be surge in current that need to be supported by the VDD core supply as per the data sheet spec (IDD max = 440mA). 

    Did you make sure your supply is clean and supports 440mA of current?

    If you increase the speed gradually i.e. IMULT = 3, 6, 10, 12, 15, 18, 20; do you see the PLL lock without getting any error?

    Regards,

    Nirav