F28M35H52C: ePWM7

I'm using the F28M35H52C1 Concerto on a custom board

I'm trying to configure ePWM7 on the C28 core but all the registers remain 0 after i run my initialize code.

ePWM1 is functional

My first guess that the registers are not being clock... ??   but I haven't found anything yet.

Any ideas where to check?

thanks

Greg

Code below:

M3:

SysCtlClockConfigSet(SYSCTL_USE_PLL | (SYSCTL_SPLLIMULT_M & 0xF) | SYSCTL_SYSDIV_1 | SYSCTL_M3SSDIV_2 | SYSCTL_XCLKDIV_4);

C28:

Note: period is calculated else where before hand

    EALLOW;
    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;           // Stop all the TB clocks
    EDIS;

    // ------------------------------------------------------------------------
    // EPWM1 - Master
    EPwm1Regs.TBPRD     = period;                    // Time-Base Period, PWM frequency = 1 / period
    EPwm1Regs.TBPHS.all = 0;                         // Time-Base Phase
    EPwm1Regs.TBCTR     = 0;                         // Time-Base Counter

    // Time-Base Clocks
    EPwm1Regs.TBCTL.bit.CTRMODE   = TB_COUNT_UPDOWN; // Count Up-Down mode: used for symmetric PWM
    EPwm1Regs.TBCTL.bit.PHSEN     = TB_DISABLE;      // Master module
    EPwm1Regs.TBCTL.bit.SYNCOSEL  = TB_CTR_ZERO;     // Sync down-stream module
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm1Regs.TBCTL.bit.CLKDIV    = TB_DIV1;
    EPwm1Regs.TBCTL.bit.PRDLD     = TB_SHADOW;       // Set load from Shadow register

    // Interrupts
    EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRD;
    EPwm1Regs.ETSEL.bit.INTEN = 1;                  // Enable INT
    EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;             // Generate INT on every event

    // ------------------------------------------------------------------------

    // EPWM7 
    EPwm7Regs.TBPRD = period;                       // Time-Base Period
    EPwm7Regs.TBPHS.all = 0;                        // Time-Base Phase
    EPwm7Regs.TBCTR = 0;                            // Time-Base Counter

    // Time-Base Clocks
    EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;  // Count-updown mode: used for symmetric PWM
    EPwm7Regs.TBCTL.bit.PHSEN = TB_ENABLE;          // Slave to EPWM1
    EPwm7Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm7Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm7Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
    EPwm7Regs.TBCTL.bit.PRDLD = TB_SHADOW;          // Set Immediate load

    // Setup shadow register load on ZERO
    EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm7Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;   // load on CTR=Zero
    EPwm7Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;   // load on CTR=Zero

    // Set Compare values
    EPwm7Regs.CMPA.half.CMPA = period+1;            // Set A LOW initially
    EPwm7Regs.CMPB = 0;                             // Set B HIGH initially

    // Set actions
    EPwm7Regs.AQCTLA.bit.CAU = AQ_SET;              // Set PWM7A on event A, up count
    EPwm7Regs.AQCTLA.bit.CAD = AQ_CLEAR;            // Clear PWM7A on event A, down count
    EPwm7Regs.AQCTLB.bit.CBU = AQ_SET;              // Set PWM7B on event B, up count
    EPwm7Regs.AQCTLB.bit.CBD = AQ_CLEAR;            // Clear PWM7B on event B, down count

    // DeadBand configuration
    EPwm7Regs.DBCTL.bit.IN_MODE = DBA_ALL;          // EPWM7A is the source for both falling-edge and rising-edge delay
    EPwm7Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;  // Both the falling-edge delay (FED) and rising-edge delay (RED) are applied to the input signals
    //EPwm7Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
    EPwm7Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;        // Active High
    EPwm7Regs.DBRED = RED_DELAY_B;                  // Set DeadBand time for rising edge
    EPwm7Regs.DBFED = FED_DELAY_B;                  // Set DeadBand time for falling edge