Part Number: TMS320F28062
Dear，
We are designing single resistance sampling in TMS320F28062 chip, when debugging the sampling points found that some sampling point's time doesn't match with we set in code. So we want to check the reason.
In our design, we configure PWM1, PWM2, PWM3, A, B channel, they will output three-phase bridge waveform, two sampling were triggered by CMPA and CMPB PWM4 values, with increasing count mode, when the counter value is equal to CMPA, trigger SOC0 sampling, when the counter value is equal to CMPB when the trigger SOC1 sampling, in two samples, we triggered EOC0 and EOC1 and call the ADC_ISR1 and ADCISR2 two interrupt function by ADCINT1 and ADCINT9 , just enter the first step of the operation before and after the two interrupt function, respectively, on the same level of GPIO in high pull and down pull Observation of sampling location through the oscilloscope. The specific waveform is shown below:
Pictured above, purple, yellow and green are three-phase bridge PWM (all A channels), the blue sampling GPIO waveform points interruption control, can be seen in the first interrupt pulled off second times in the Euphrates, in our algorithm, is two times of sampling respectively in three-phase duty middle rise, such as above this waveform, the blue line should be pulled in purple yellow, yellow green in the middle Euphrates, in most cases is indeed the case, but from time to time there will be one or two or three abnormal points, blue waves rising and falling edge after all a lining interval (above arrow to the right, the blue cross the yellow line.).
Before I code each time for each PWM channel CMPA and CMPB will be assigned the value assigned by the temporary storage, and after all preserved in the same period of PWM1, PWM2, PWM3 and PWM4, a total of 4 sampling points of CMP were compared, found that assigned to the register value, and no crossing situation.
This phenomenon, cause we now sampled current value will appear larger error (or a sampling point directly, wrong) in the test method, program configuration allows interrupt nesting, and for the first time priority is higher than second times, therefore, personal feel is not interrupt on a cycle of second times before the end of this cycle the first interrupt is delayed, leading to this phenomenon, even if it should be a continuous time delay, but not with a two time interval?
Even if we increase the interval between the rising edge 22 of the three-phase drive PWM to ensure that the sampling point has enough time intervals of several US between the front and the back sides, the phenomenon of "cross over" will still appear in the oscilloscope observation.
I don't know if the question is has some relation with below picture？ Pls help give some advice，Great thx.
