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F28M35H52C: Concerto F28M35x Power Domain

DO-Pro
Intellectual 610 points

Part Number: F28M35H52C
Other Parts Discussed in Thread: CONTROLSUITE

Hi,

I have several questions regarding F28M35x power pins.

1. First off, the datasheet for Concerto family calls out pin 91 as NC (no connect) while schematic diagram for Concerto DIMM100 Control Card in controlSUITE, file 514982E_CONCERTO_DIMM100_RELEASE2_00_ALLEGRO_DEC_17_2011.pdf,  shows it as one of VDD12 power pins. So what is actually correct? Should that pin be left unconnected or should I handle it as 1.2V dc power pin? I searched through the forum and the only single relevant topic I found is left unanswered. Please clarify details of this pin for me.

2. The same above mentioned schematic shows 3.3V dc power pins individually decoupled by LC-filters. It seems to be somewhat different from the approach typically taken by most chip manufacturers, where multiple power pins are all connected together while still decoupled by individual capacitors. Is using individual LC-filtering a lab-verified much needed approach or is it just a general advice? The real estate on the board is highly limited so reducing parts count would certainly help.

3. Are pins in 3.3V dc domain connected together internally? If not, would it be possible to provide more details as to what internal circuits and/or GPIOs each specific 3.3V power pin is responsible for?

4. Are pins in 1.2V dc domain connected together internally? If not, would it be possible to provide more details as to what internal circuits each specific 1.2V power pin is responsible for? Is individual LC-filtering required on these pins similar to that on 3.3V power pins above?

Thank you for your support.

Regards, Michael

  • 0
    Intellectual 610 points

    Hi,

    Is there any chance of having my questions answered any time soon?

    Thank you, Michael

  • 0 in reply to DO-Pro
    Guru 30330 points
    Hello Michael,

    1. The datasheet is correct. Pin 91 is an NC pin and can be left unconnected. This seems to be a carryover from some internal design work and the board has not been revised since that time. I will file a ticket on the board for the schematic to be updated. This will not guarantee that the issue/confusion will be fixed, but it will be on the list if there ever is a need for a revision.

    2. The Ferrite beads are not required. The beads are added to help mitigate noise being coupled between the device/analog circuits and main PSU for the board. They may have been added as extra protection, but again not required. The decoupling Caps for each pin are required. please see this post restating this fact: e2e.ti.com/.../727896

    3./4. We do not share this information about the internal power connections. All VDDIO pins, VDDA, and VDD pins should be connected to the same respective supplies. We do not support having VDDIO or any supply rail be powered with multiple distinct supplies. VDD pins do not require the ferrite beads (see #2)

    I hope that this answers your questions.

    Regards,
    Mark
  • 0 in reply to Mark Labbato
    Intellectual 610 points

    Mark,

    Thank you for your response.

    2. So with regard to the ferrite beads, it seems that these beads could be instrumental but having some quantitative data would certainly help to resolve performance-vs-PCB-real-estate tradeoff. Does TI have any noise measurement plots with and without these beads or other data that could be shared with engineering community in this regard?

    3./4. When internal regulators are ENABLED, is it still required to connect together respective VDD12 / VDD18 pins or would it be sufficient to keep them separated but with individual decoupling capacitors still connected? If pins still must be connected together, what's a correct approach to size connecting traces from the current flow prospective? Should they be massive local copper polygons for full Iq current capabilities or would just regular 5 or 8 mil traces be OK?

    Please clarify this stuff for me.

    Regards, Michael

  • 0 in reply to DO-Pro
    Guru 30330 points
    Michael,

    2. We do not have any quantitative data here to show the pros and cons of such a configuration. Looks like the best guide I have been able to find is this: www.ti.com/.../szza009

    3. each VDD pin still requires a minimum capacitor placed as close to the pin as possible. standard trace sizing is sufficient. The caps are there to handle the high frequency loads on the supply. They will supply small charge and the power plane can provide lower frequency support. Local copper pours with additional bulk caps are generally recommended, but again, the aforementioned app note provides some guidance.

    Regards,
    Mark
  • 0 in reply to Mark Labbato
    Intellectual 610 points

    Mark,

    Thank you for that application note. Very helpful and informative.

    Regarding Q3, you didn't say so explicitly but it sounds like all VDD12 pins still have to be tied together even with internal regulator enabled. And by extension, I assume it's also true for VDD18 pins. Could you please confirm or disprove?

    Thank you, Michael

  • 0 in reply to DO-Pro
    Guru 30330 points
    Yes, the capacitance on the VDD supplies are used to help stabilize the Internal Regulator. The layout should essentially be the same between internal regulator and external supply case with the exception of the connection to an external supply. Meaning, all VDD12 pins should be tied together with sufficient decoupling caps to ground. Same thing for the VVDD18 pins.

    Regards,
    Mark
  • 0 in reply to Mark Labbato
    Intellectual 610 points
    Thank you, Mark.
    This answers my question.

    Regards, Michael