The below discrip is from SPRUH18E. it is for ADCINTFLG and ADCINTFLGCLR discription. What is right?
Clears respective flag bit in the ADCINTFLG register. If software tries to set this bit on the same
clock cycle that hardware tries to set the flag bit in the ADCINTFLG register, then hardware has
priority and the ADCINTFLG bit will be set. In this case the overflow bit in the ADCINTOVF register
will not be affected regardless of whether the ADCINTFLG bit was previously set or not.
vs
Boundary condition for clearing or setting flag bits: If hardware is trying to set bit while
software tries to clear the bit in the same cycle, the following will take place:
1. SW has priority, and will clear the flag
2. HW set will be discarded, no signal will propagate to the PIE form the latch
3. Overflow flag or condition will be generated
