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TMS320F28035: How to set LOADAMODE/LOADBMODE valule in EPWM module?

qiu wei
Intellectual 315 points
Part Number: TMS320F28035

Hi 

I ask for the answer How to set LOADAMODE/LOADBMODE valule in EPWM module, Load on CTR = Zero, Load on CTR = PRD, or Load on either CTR = Zero or CTR = PRD?

What is the major consideration when set the LOADAMODE/LOADBMODE valule? Thank you.

  • 0
    TI__Mastermind 27200 points
    The LOADxMODE fields allow the user to define specific points in the PWM pattern when active register updates take place. This feature ensures that compare register reloads are deterministic within each switching cycle.

    For example, consider the case where you are modulating the duty cycle of a simple PWM pattern from an interrupt which is triggered on a CTR=zero event. The ISR takes a finite number of cycles to execute, so if your newly computed duty cycle is greater than this number, the update can happen immediately inside the ISR and the new duty cycle takes effect in the same PWM cycle.

    However, if your new duty cycle is less than the ISR cycle count, the PWM timer will already have passed that value when the new compare value is written and your PWM will keep the older duty value in that cycle. Forcing shadow-to-active updates at specific points in the PWM pattern avoids
    inconsistent or erroneous PWM updates. Separately defining A and B comparator updates provides flexibility when complex PWM patterns are required.

    Regards,

    Richard
  • 0 in reply to Richard Poley
    Intellectual 315 points
    Thank you very much, Richard.

    Below is the PWM_2ch_UpDwnCnt_CNF function in digital power libs. We can see the EPWMA AQ set to AQ_SET/AQ_CLEAR,

    and the LOADAMODE set to CC_CTR_ZERO, while the EPWMB AQ set to AQ_CLEAR/ AQ_SET, and the LOADABODE set to CC_CTR_PRD，

    is the LOADxMODE set relevant to AQ set?

    ///////////

    void PWM_2ch_UpDwnCnt_CNF(int16 n, int16 period, int16 mode, int16 phase)
    {
    // Time Base SubModule Registers
    (*ePWM[n]).TBCTL.bit.PRDLD = TB_SHADOW; // set Shadow load
    (*ePWM[n]).TBPRD = period/2; // half-period due to up-down count
    (*ePWM[n]).TBPHS.half.TBPHS = 0;
    (*ePWM[n]).TBCTR = 0;
    (*ePWM[n]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
    (*ePWM[n]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
    (*ePWM[n]).TBCTL.bit.CLKDIV = TB_DIV1;

    if(mode == 1) // config as a Master
    {
    (*ePWM[n]).TBCTL.bit.PHSEN = TB_DISABLE;
    (*ePWM[n]).TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // sync "down-stream"
    }
    if(mode == 0) // config as a Slave (Note: Phase+2 value used to compensate for logic delay)
    {
    (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
    (*ePWM[n]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

    if ((0 <= phase)&&(phase <= 2))
    {
    (*ePWM[n]).TBPHS.half.TBPHS = (2-phase);
    (*ePWM[n]).TBCTL.bit.PHSDIR = TB_UP; // set to count up after sync
    }
    else if ((2 < phase)&&(phase <= period/2+2))
    {
    (*ePWM[n]).TBPHS.half.TBPHS = (phase-2);
    (*ePWM[n]).TBCTL.bit.PHSDIR = TB_DOWN; // set to count down after sync
    }
    else if ((period/2+2 < phase)&&(phase <= period))
    {
    (*ePWM[n]).TBPHS.half.TBPHS = (period-phase+2);
    (*ePWM[n]).TBCTL.bit.PHSDIR = TB_UP; // set to count up after sync
    }
    }

    // Counter Compare Submodule Registers
    (*ePWM[n]).CMPA.half.CMPA = (period/2)/2; // set duty 50% initially
    (*ePWM[n]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    (*ePWM[n]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    // Action Qualifier SubModule Registers
    (*ePWM[n]).AQCTLA.bit.CAU = AQ_SET;
    (*ePWM[n]).AQCTLA.bit.CAD = AQ_CLEAR;

    // Counter Compare Submodule Registers
    (*ePWM[n]).CMPB = (period/2)/2; // set duty 50% initially
    (*ePWM[n]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    (*ePWM[n]).CMPCTL.bit.LOADBMODE = CC_CTR_PRD;
    // Action Qualifier SubModule Registers
    (*ePWM[n]).AQCTLB.bit.CBU = AQ_CLEAR;
    (*ePWM[n]).AQCTLB.bit.CBD = AQ_SET;
    //(*ePWM[n]).AQCTLB.bit.CBD = AQ_CLEAR;//Turn off PWMB....test*****************
    }
  • 0 in reply to qiu wei
    TI__Mastermind 27200 points

    Hi Qui,

    LOADxMODE is independent of AQ set or clear: it just determines when in each PWM cycle the shadow-to-active load takes place.  The AQ settings determine the action at the pin on a compare match.

    In the code you posted, CMPA is loaded from its' shadow on CTR=0, while CMPB is loaded from its' shadow on CTR=PRD.  The AQ settings do not change: A output is active high, while B output is active low; so they form a complementary pair. The PWM pattern is something like the attached.  The only thing the LOADxMODE bits are doing is affecting the shadow-to-active updates.

    Regards,

    Richard

    6765.ePWM.pdf