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Tool/software: Code Composer Studio
Hi
i am working for generating 3PWM waves. i am using EPW1,2,3 .i can get the 3 waves but i want phase shift in PWM2 and 3 with respect to PWM1
i refereed the ePWM-reference guide which given by TI...i used the example 13...figure 68
Hi Kudithi,
For phase shift, on EPWM 2 & 3 you will want to enable phase loading via the TBCTL[PHSEN] bit. The value you program into each the TBPHS register of EPWM2 & EPWM3 will then be loaded into the TBCTR on a sync or similar event.
Regards,
Kris
thanks you Kris
i did it but i con't get it ...this my code please go through it
#include "F28x_Project.h"
#define PWM_Prd 5000;
#define Phi 500;
#define Phi2 50;
//Function Prototypes
//
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
__interrupt void epwm1_isr(void);
__interrupt void epwm2_isr(void);
__interrupt void epwm3_isr(void);
//
// Main
//
void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
InitSysCtrl();
//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to its default state.
//
// InitGpio();
//
// enable PWM1, PWM2 and PWM3
//
CpuSysRegs.PCLKCR2.bit.EPWM1=1;
CpuSysRegs.PCLKCR2.bit.EPWM2=1;
CpuSysRegs.PCLKCR2.bit.EPWM3=1;
//
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the F2837xD_EPwm.c file
//
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
DINT;
//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
InitPieCtrl();
//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
InitPieVectTable();
//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.EPWM1_INT = &epwm1_isr;
PieVectTable.EPWM2_INT = &epwm2_isr;
PieVectTable.EPWM3_INT = &epwm3_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
//
// Step 4. Initialize the Device Peripherals:
//
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
EDIS;
InitEPwm1Example();
InitEPwm2Example();
InitEPwm3Example();
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
EDIS;
//
// Step 5. User specific code, enable interrupts:
// Initialize counters:
//
//EPwm1TimerIntCount = 0;
// EPwm2TimerIntCount = 0;
//EPwm3TimerIntCount = 0;
//
// Enable CPU INT3 which is connected to EPWM1-3 INT:
//
IER |= M_INT3;
//
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
//
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
//
// Enable global Interrupts and higher priority real-time debug events:
//
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
//
// Step 6. IDLE loop. Just sit and loop forever (optional):
//
for(;;)
{
asm (" NOP");
}
}
__interrupt void epwm1_isr(void)
{
EPwm1Regs.TBPHS.bit.TBPHS = 0;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
__interrupt void epwm2_isr(void)
{
EPwm2Regs.TBPHS.bit.TBPHS = 0;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
__interrupt void epwm3_isr(void)
{
EPwm3Regs.TBPHS.bit.TBPHS = 0;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
void InitEPwm1Example(void)
{
EPwm1Regs.TBPRD = 1250; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm1Regs.TBCTR = 0; // Clear counter
// // Set Compare values0 //
EPwm1Regs.CMPA.bit.CMPA = 1250; // Set compare A value
EPwm1Regs.CMPB.bit.CMPB = 1250;
// // Setup counter mode //
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = 0;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// // Set actions //
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up
// count
EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // Clear PWM1A on event A,
// down count
EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Set PWM1B on event B, up
// count
EPwm1Regs.AQCTLB.bit.ZRO= AQ_SET; // Clear PWM1B on event B,
// down count
// // Interrupt where we will change the Compare Values //
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
void InitEPwm2Example(void)
{
EPwm2Regs.TBPRD = 1250; // Set timer period 801 TBCLKs
EPwm2Regs.TBPHS.bit.TBPHS = 500; // Phase is 0
EPwm2Regs.TBCTR = 0; // Clear counter
// // Set Compare values0 //
EPwm2Regs.CMPA.bit.CMPA = 1250; // Set compare A value
EPwm2Regs.CMPB.bit.CMPB = 1250;
// // Setup counter mode //
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // enable phase loading
EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN;
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// // Set actions //
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up
// count
EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // Clear PWM1A on event A,
// down count
EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Set PWM1B on event B, up
// count
EPwm2Regs.AQCTLB.bit.ZRO= AQ_SET; // Clear PWM1B on event B,
// down count
// // Interrupt where we will change the Compare Values //
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
void InitEPwm3Example(void)
{
EPwm3Regs.TBPRD = 1250; // Set timer period 801 TBCLKs
EPwm3Regs.TBPHS.bit.TBPHS = 500; // Phase is 0
EPwm3Regs.TBCTR = 0; // Clear counter
// // Set Compare values0 //
EPwm3Regs.CMPA.bit.CMPA = 1250; // Set compare A value
EPwm3Regs.CMPB.bit.CMPB = 1250;
// // Setup counter mode //
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // enable phase loading
EPwm3Regs.TBCTL.bit.PHSDIR = TB_DOWN;
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// // Set actions //
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up
// count
EPwm3Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // Clear PWM1A on event A,
// down count
EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Set PWM1B on event B, up
// count
EPwm3Regs.AQCTLB.bit.ZRO= AQ_SET; // Clear PWM1B on event B,
// down count
// // Interrupt where we will change the Compare Values //
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
