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TMS320F28075: I2C Data setup timing issue

Andy Snawerdt
Intellectual 2380 points
Part Number: TMS320F28075


Hi Team,

I am working with a customer who is using the TMS320F28075 as a slave device.

They notice a violation of the 250ns setup time required for SDA, before SCL rises. Note that they are running the I2C bus at 100 kHz.

This occurs when their master performs a writeRead with the TMS320F28075. An example of where the error occurs in the data stream is shown below:

Below is a scope of the timing violation. The points at which SDA (in blue) crosses VIH and SCL (in yellow) crosses VIL are marked in red. The setup time between these points is either zero or negative due to the rising edges occurring too close together. Note that they are using 4.7K pullups on these lines.

 

Do you happen to know if this kind of behavior has been seen before when the TMS320F28075 is in slave mode? If not, do you know if there is a way to fix this timing violation?

Regards,

Andy

  • 0
    TI__Mastermind 45606 points
    Hello Andy,

    Is this issue only seen on the first bit of the byte being read and only when it is a 1?

    Can you confirm that the customer has set the I2C module clock to be between 7-12 MHz, the timing specs in our datasheet assume this requirement is met. (Look into I2caRegs.I2CPSC register for how to set this if needed)

    If the correct clocking is set could you have the customer send a screen capture showing the entire SCL high/low/high cycle to look at the slave's SDA hold time? A capture of the entire byte being read might b helpful as well.

    Thanks,
    Kevin
  • 0
    TI__Guru 55700 points
    Andy,

    The setup you are talking about is 100ns. Based on the snapshots attached, it looks like you have 1us time-base. Can you try zooming in and check whether you have 100ns setup time?

    Regards,
    Manoj