TMS320F28067: F28067 ADC issues

Jordan Zhou said:

1) ADC pin voltage: pin B0 is always 0 or 1mV. Pin B3 and B7, there's about 39mV. Where does it come from? Do we need to separate B3 and B7?

The ADC sample & hold capacitor (Ch) is shown in this model from the datasheet.  The Ch capacitor can carry charge between SOCs.  The ACQPS must be long enough to allow the Ch cap to fully charge or discharge based on the source resistance (Rs) of the external signal.  In the case where Rs is 10kΩ, the ACQPS would need to be very large to discharge a worst-case carryover charge of 3.3V -- try the maximum supported ACQPS value to see if it helps.

Jordan Zhou said:

2) ADC offset calibration and accuracy. I did several test and found that: 

2.1) ADC TRIM factory value from ROM is 0x0B, after sequential conversion, ADC result for B0 and B5 are 2 and 3 (these should be right); B3 is 0x6B; B7 is 0x4E. (These are wrong)

2.2) ADC TRIM is calibrated, with a new value 0x1EB, after sequential conversion, ADC result for B0 and B5 are always 0 (these should be wrong, although ADC result is 0. I tried to changed the TRIM by hand like 0x1FB or 0x08, B0 and B5 are still 0); B3 is 0x4C; B7 is 0x2E. 0x2E means 37mV, which is the real pin voltage 39mV.

2.1) and 2.2) are conflict. With different TRIM values, different channels are right, others are wrong.

3) ADC channel-to-channel variation: from test 2), we found the large variation of B3 and B7, although they are physically connected. If they are changed to different SOC, the result is more or less the same. Or B3's result is larger than B7's, or B7's is larger, or they are very close.

Rs and ACQPS should be modified on B3 and B7 for correct ADC results.

Rs is modified, without any improvement.
ACQPS can help. One question is, how to define the right ACQPS? Any rules?

Today I did some other tests, and found that, the factory offset was good, but the full scale gain was bad. No matter internal reference or external reference, the value in ADCREFTRIM can't provide a good gain. Take 3.3V as an example, the result value was only 4027, instead of 4095. Is this gain normal in our datasheet?

Another question, enable or disable overlap, the result varies a lot. For example, 63mV on the ADC pin, 10 ACQPS, when overlap is enabled, ADC result is 47; if disabled, it's 70. When 6 ACQPS, the results are the same 73. Why is it?

Thanks a lot.
Br, Jordan

Jordan,

It should be possible to simulate the ADC input pin model to figure out how long it will take for the S/H capacitor to settle. Some good starting values would be 280ns for a 1kΩ Rs, and 2.3us for a 10kΩ Rs.

How is the 3.3V source provided?  Is it a clean, low-noise source?  Can you capture a series of conversions to see if there is noise spread in the results?

According to the datasheet, the ADC gain error should be less than what you are seeing:

Can you confirm that the ADCCLK is 45MHz or lower, and that the software configuration is taking care of the ADC advisories?

-Tommy

Tommy,

Thanks for your info.

Actually, all of these tests were done.

1) Different ACQPS result to different ADC result.  

B3 and B7 are connected together, through 1K to AGND, different ADC result values. B4 pin's voltage is 63mv. The right ADC value should be 78.

2) Power supply is quite clear. Single low power board is seperated from their system. 5V is supplied from USB port.

3) ADC data are saved in a list and then do the calculation. No noise is founed.

4) Current 45MHz is used. 25.5MHz is also tried, there's no improvement.

Thanks a lot.

Br, Jordan

Jordan Zhou said:

1) Different ACQPS result to different ADC result.  

B3 and B7 are connected together, through 1K to AGND, different ADC result values. B4 pin's voltage is 63mv. The right ADC value should be 78.

Do you have a schematic that you can share for the Bx ADC pins and how the B4 signal is supplied?

Jordan Zhou said:

2) Power supply is quite clear. Single low power board is seperated from their system. 5V is supplied from USB port.

For the 3.3V source, I was referring to the reference voltage that was used to measure gain error, not the VDDA supply.

Jordan Zhou said:

3) ADC data are saved in a list and then do the calculation. No noise is founed.

So all of the conversions are about +/- 3 LSB of each other?

Jordan Zhou said:

4) Current 45MHz is used. 25.5MHz is also tried, there's no improvement.

Does the frequency change shift the ACQPS behavior at all?

Hi,

Here's the sch of ADC pins. The reference is from external 3.3V, instead of VDDA.

In the list, all of the conversions are less than +/-3 LSB.

With 25.5MHz, here's the result, overlap=1:

ACQPS=8, B3=22, B7=13, B4=78.

ACQPS=10, B3=13, B7=8, B4=79.

ACQPS=13, B3=3, B7=0, B4=74.

Br, Jordan

Jordan,

A sampling window of 2.3us for B3 and B7 would require an ACQPS setting of 58 at 25.5MHz. An insufficient ACQPS setting will contribute to crosstalk between a conversion on B3 and B7 vs prior conversions.

What does the V_ISO_M path on B4 look like? How is the impedance and bandwidth?

How was gain error measured?

-Tommy

Tommy,

Here's the result of 2.3us sampling window:

1) When ADCOFFTRIM is calibration under ACQPS=6, it's 0x01FB.

B3 and B7's ADC result is 0 with ACQPS=0x33.

1) When ADCOFFTRIM is calibration under ACQPS=8, it's 0x0002.

B3 and B7's ADC result is 5 with ACQPS=0x33.

B4's sch is as:

When ADCOFFTRIM is calculated with ACQPS=8, with ACQPS=8 sampling window, B4's result is very close to the voltage of the pin 64mV.

The Gain is about 0.016156, for 4095, it's about 66LSB.

Br, Jordan

Jordan,

It looks like the B3 & B7 conversions are much better with sufficient ACQPS settling.

We have seen situations where different PCBs and (less commonly) ACQPS settings can produce unique offset errors.  It looks like this may be the case here.  If needed, it should be possible to create a look-up table of offset correction per ACQPS setting and post-process the ADC conversions with software.

The 2kΩ series resistor and 10nF capacitor on V_ISO_M may require significant ACQPS settling time (~200us).  If this is a high bandwidth path, it might be a good idea to reduce the capacitance so that the node can react faster to ADC S/H charging.

-Tommy

Tommy,
Is it an issue of ADC?
Customer needs a reply and a solution.
Thanks a lot.
Br, Jordan

Jordan,

I would consider this to be related to the ADC Offset Self-Recalibration advisory.

Periodic calibration using the same ADC settings as the use-mode settings should provide the offset error to remove.

-Tommy

Tommy,
We are working with customer on the RC of ADC pins.
But, according to our test, offset recalibration can't solve the issue, as we did several test to change the RC, there's still the issues.
Br, Jordan