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CCS/LAUNCHXL-F28377S: why different sampling clock have different sample的 result？

user3588080
Intellectual 420 points
Part Number: LAUNCHXL-F28377S


Tool/software: Code Composer Studio

Use 28377 sampling adc single-ended mode, when ADCCTL2. PRESCALE set sampling clock divider coefficient is different, ACQPS is same , the sampled result is different, and  clock divider coefficient is same,with different ACQPS, result also slightly different, could you tell me why?

  • 0
    TI__Guru 60865 points
    Hi '8080

    The results should be mostly the same with different PRESCALE and same ACQPS as long as the ADCCLK is < 50MHz. If ADCCLK > 50MHz based on the SYSCLK and PRESCALE setting, the ADC may not work well or be accurate.

    With the same ADCCLK but different ACQPS settings, the S+H window will change. If you have a well-buffered signal being driven in on a short trace from a high-speed and low-noise op-amp with reasonably low C (say 100pf) and low R (say 50 ohms), the the sampled signal shouldn't change much for ACQPS that give S+H > minimum S+H, which is 75ns. In other cases, the sampled signal may change as the signal is allowed more time to settle. This will be especially pronounced with high R or C, long traces or cables, or if the signal is being buffered by an op-amp with slower BW.

    Note that both of the above will change the sample rate if using back-to-back conversions, so this will change the sampled waveform if it is AC (or if it is DC, but the noise isn't strictly gaussian). if the sampling is evenly spaced (e.g. ePWM driven) the sampling rate should be the same as long as the trigger pulses are sufficiently far apart to allow the sample to complete between triggers.