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Compiler/TMS320F28377D: Frequent access of IER during runtime

Amtech
Genius 4595 points

Part Number: TMS320F28377D
Other Parts Discussed in Thread: C2000WARE

Tool/software: TI C/C++ Compiler

Dear Sir,

I am using TMS320F28377D for my inverter application. I am frequently using IER register to enable/disable interrupts in software. For example on high priority control loop, we are disabling all other communication related interrupt groups through IER.

Now my query is:

What i am doing? Disabling certain group of IER before going into high priority control loop and after execution of it, re-enable IER. So, If IER is disabled and that particular group generate interrupt then what will happen at the time of re-enable IER? Is interrupt occur? (If yes, what is the maximum number of interrupt can be generated) What will happen in case of multiple interrupt ?


Is this right method to write control software? If not then please suggest, How to take care of this situation? Is there any possibilities of skip interrupt(in case on multiple interrupt from same group)?

Thanks and Regards,

Maulik Timbadiya

  • 0
    TI__Mastermind 27200 points
    Maulik,

    Interrupts are sampled at the CPU clock frequency. When you re-enable the IER line, if there are multiple PIE interrupts pending on that line the lowest number will be serviced first, followed by the next lowest. If multiple interrupts have occurred from the same peripheral since its IER bit was last enabled, when you re-enable you will only get one interrupt going to the CPU. The others will be lost.

    If you think there is a risk of that happening you must manage the interrupt timing carefully. Typically, a low priority ISR will limit the time that higher priority interrupts are masked to just protect the context save & restore, by re-enabling higher priority interrupts inside the ISR. There is an example of interrupt prioritization in the device specific header file in C2000Ware. If you have the latest version installed at the default location on your hard drive, the example will be at:

    C:\ti\c2000\C2000Ware_1_00_02_00\device_support\f2837xd\examples\cpu1\sw_prioritized_interrupts

    Regards,

    Richard
  • 0 in reply to Richard Poley
    Genius 4595 points
    Dear Richard,

    Thank you for your prompt response. What will happen in below mentioned steps:
    1. IER enable and no interrupt is pending.
    2. After set IER = 0 and suppose my SCI peripheral receive data and it try to generate interrupt.
    3. IER enable.

    Any interrupt occur when IER becomes enable on above particular steps? what will happen with SCI interrupt ? Is it skip?

    Regards,
    Maulik Timbadiya
  • 0 in reply to Amtech
    TI__Mastermind 27200 points

    Dear Maulik,

    If no other interrupts occur during step 2, sand the PID has been configured properly, the CPU should take the SCI interrupt when you enable it at the IER.

    Are you seeing different behaviour?

    Regards,

    Richard

  • 0 in reply to Richard Poley
    Genius 4595 points
    Dear Richard,

    I am just confirming my understanding over it.
    You mean to say that corresponding IFR will set even if IER is disabled. Right?
    And it will generate interrupt when IER will enable?

    Regards,
    Maulik
  • 0 in reply to Amtech
    TI__Mastermind 27200 points

    Dear Maulik,

    Yes, that is correct.  IFR is before IER.  INTM disables all interrupts (see attachment).

    Regards,

    Richard

    maskable core interrupts.pdf

  • 0 in reply to Richard Poley
    Genius 4595 points
    Thanks Richard.

    I marked this post as answered.
    Have a good day.

    Regards,
    Maulik