CCS/TMS320F28377S: SCI receive interrupt is working with debugger only

Part Number: TMS320F28377S
Other Parts Discussed in Thread: C2000WARE

Tool/software: Code Composer Studio

I am working in TMS320F28377S microcontroller and CCS 6.2. I am using Black Hawk 510L JTAG EMULATOR. My receive interrupt is working in debugging only. Transmit operation are working fine. My initialisation code is given below. I am using scic and not using tx interrupt

void main(void)

{

    InitSysCtrl();

DINT;
InitPieCtrl();

IER = 0x0000;
IFR = 0x0000;

InitPieVectTable();

EALLOW;
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieVectTable.ADCA1_INT = &adc_isr;
PieVectTable. SCIC_RX_INT = &scicRxFifoIsr;
EDIS;

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
EDIS;

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
EDIS;

GPIO_SetupPinMux(89, GPIO_MUX_CPU1, 6);
GPIO_SetupPinOptions(89, GPIO_OUTPUT, GPIO_ASYNC);

GPIO_SetupPinMux(90, GPIO_MUX_CPU1, 6);
GPIO_SetupPinOptions(90, GPIO_INPUT, GPIO_PUSHPULL);

init_serial_c();

// Enable CPU INT3 which is connected to EPWM1-3 INT:

IER |= M_INT8;

PieCtrlRegs.PIEIER8.bit.INTx5 = 1;   

EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

while(1)

 {

  scic_msg("AT"); ms(1); scic_xmit(0x0D);

  ms(250);

 }

} 

  volatile char rx_sci_c,counter=0,test_arrar[160];

__interrupt void scicRxFifoIsr(void) //GSM Modem
{
GpioDataRegs.GPBTOGGLE.bit.GPIO41=1;

rx_sci_c=ScicRegs.SCIRXBUF.all;

if(counter>=120) counter=0;

else test_arrar[counter]=rx_sci_c;

counter++;

// write_que(rx_sci_c);

ScicRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag
ScicRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag
PieCtrlRegs.PIEACK.all= PIEACK_GROUP8 ; // Issue PIE ack
}

void init_serial_c(void)
{
gsm_data.gsm_buffer_error=false; //set gsm buffer flag to false

EALLOW; // This is needed to write to EALLOW protected registers

// PieVectTable.SCIC_RX_INT = &scicRxFifoIsr;
// PieVectTable.SCIC_TX_INT = &scicTxFifoIsr;
EDIS; // This is needed to disable write to EALLOW protected registers

EALLOW;

PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER8.bit.INTx5 = 1; // PIE Group 9, INT1 rx interrupt enable
//PieCtrlRegs.PIEIER8.bit.INTx6 = 1; // PIE Group 9, INT2 tx interrupt enable

scic_fifo_init();

//IER |= M_INT8;
//IER = 0x100; // Enable CPU INT
//EINT;
// EINT;
// ERTM;
// EDIS;
}

void scic_fifo_init(void)
{
//
// Note: Clocks were turned on to the SCIA peripheral
// in the InitSysCtrl() function
//
EALLOW;
ScicRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback
// No parity,8 char bits,
// async mode, idle-line protocol
ScicRegs.SCICTL1.all = 0x0003; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
ScicRegs.SCICTL2.all = 0x0003;
//ScicRegs.SCICTL2.bit.TXINTENA = 1;
ScicRegs.SCICTL2.bit.RXBKINTENA = 1;

//
// SCIA at 4800 baud
//
ScicRegs.SCIHBAUD.all =0x0005; // 0x0002;
ScicRegs.SCILBAUD.all =0x0016; // 0x008B;

ScicRegs.SCICTL2.bit.RXBKINTENA=1;

ScicRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset

}