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TMS320F28035: Phase shifting of PWM channels with variable frequency missing compare event

Siddharth Sharma1
Intellectual 445 points

Part Number: TMS320F28035

Hi all,

I am are using phase shift / sync on 28035 PWM channels with variable frequency in up-count mode. My application is PSFB where EPWM2 is slave and phase shifted by EPWM1 which is master one. I am varying PWM frequency from 95khz to 105khz by varying its period . Sysclock freq used is 60 MHZ..

But i am observing PWM2 missing compare event (CMPA) and thus becoming abnormal(see pic attached- Green is PWM2 and Blue is EPWM1).This behavior is only observed during No load mode of PSFB (when TBPHS value becomes nearly to 0). I am not able to understand as why compare event is getting missed. Anyone please guide me? 

 Sir any views on it? I have read lot of answers of yours but could not find solution for this problem...Please help me

  • 0
    TI__Genius 10820 points
    Hi Siddharth,

    There are two things you should do to avoid this issue.

    1. Always keep the slave PWM period value 1 count less than the master PWM period.

    2. Everytime you change the frequency from high freq to low freq, make sure the new CMP register value is not in-between the old phase value and the new phase value. If it is, change it to new PHS value +1. You must change the CMP value back to desired value in the next switching cycle.

    If above does not solve the issue, please pay close attention to where registers are getting updated in your code with respect to the PWM switching cycle. You can refer to some of my older posts for details on this.

    I hope this helps.
    Hrishi
  • 0 in reply to Hrishi Nene
    Intellectual 445 points
    Hi Hrishi Sir,

    Since i am changing CMP value from 285 to 315 always and my TBPHS value always remain around Zero value. So this is not possible at all that CMP value is between old phase value and new phase value.

    Can you suggest something as how to see the updation of registers(especially TBPHS and TBCTR) during this event getting occurred?
  • 0 in reply to Siddharth Sharma1
    TI__Mastermind 42195 points
    Siddharth,
    A few thoughts I had: Are you doing any data validation? Possibly checking that the value loaded into TBPHS is >=0 and <PWM_Period...

    Is it possible that you are writing a negative value to TBPHS? This could cause the TBCTR value to never reach your compare event.

    Regards,
    Cody
  • 0 in reply to Cody Watkins
    Intellectual 445 points

    Hi Cody,

    Yes i am validating the data.I have verified that the phase value that is being loaded is never less than 0 and also never greater than PWM_period.  

    One interesting observation i observed but could not able to connect how it is not making epwm to miss events.

    I have made TBPHS value to constant 1. Then, implemented logic to change frequency by changing Pwm period by 6 ( 600 to 606) every cycle(20 us). So my frequency step is 6. Then if i am loading (Period - 6) in epwm2 module (slave module) then error is not happening. 

    With TBPHS = 1, I also made configuration by making freqstep = 1 and (Period - 1) in slave module , then also error is not happening, But in same configuration if i made freqstep = 6 then error(pwm getting elongated) starts happening. 

    So here i am thinking that rate at which period is getting changed has some relation with delay we induce in slave pwm configuration.

    Note :- Both period and phase are changed at same rate(20 us) inside one ISR.

    Thanks

    Siddharth