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TMS320F28069: Watchdog reset question

Huihuang Chen
Expert 4060 points
Part Number: TMS320F28069


Hi Champ;

Customer  placed a 1uF capacitor between XRS and VSS for noise filtering and found the watchdog can reset the CPU normally under 25 degree, but when the amibent temperature go to 65 degree, the  watchdog reset cannot  CPU .

From the datasheert we know this capacitor should be 100 nF or smaller.

 Customer wonder  anything changed inside the chip  under high temperature ? could you help on this question?

  • 0
    TI__Guru* 95315 points
    65'C is well within the operating temperature range, so there should be no issues.

    How is the reset generated by the WD? Is a 'bad key' written to the WDCR register or is the WD counter allowed to overflow?

    How is the decision made when to generate the reset?

    I wonder if some other component on the board is affected by the heat.
  • 0 in reply to Hareesh Janakiraman
    TI__Expert 4060 points

    Hi Hareesh,

    Thanks a lot for your reply!

    This is very sample SW for testing purpose, customer will toggle the LED around 500ms, then will enable the Watchdog  and will not written the data to the WDCR, so the WD counter will overflow and the CPU will be reset by WD.

    under room temperature ,The WD will reset CPU periodiclly and  the period  is more 500ms, which can be observed by the XRS pin, but under 65'C we can found the XRS will be go low level periodiclly and the period is around 13.1ms.

    We have comfirmed both VDD,VDDIO, XCLKIN are normal under 65'C.

    After change the capacitor to 100nF ,under 65'C,The WD can reset CPU periodiclly and  the period  is more 500ms.

  • 0 in reply to Huihuang Chen
    TI__Guru* 95315 points
    Huihuang,
    Your post is confusing. You are bringing 2 variables into the picture (Capacitor value and temperature). 13.1 mS is the default WD timeout frequency. If you take a part with erased flash and power it up, you will see the -XRS pin toggling at that rate (OSCCLK/512/256 --> 10 MHz/512/256 = 76.29 Hz or 13.1 mS).

    I presume there is some code in the flash in which WD is initially disabled for 500 mS, LED toggled, WD enabled and allowed to overflow, which would reset the device.

    A high valued capacitor may not allow the -XRS pin to be driven all the way low within the duration of the WD reset (512 OSCCLK cycles --> 51.2 uS). However, you should still a "dip" in the waveform. Please provide the status and oscilloscope captures for the following cases:

    With 100 nF capacitor:
    At 25'C:
    At 65'C:

    With 1 uF capacitor:
    At 25'C:
    At 65'C:

    Please review this Wiki page: processors.wiki.ti.com/.../WDFlag_on_Piccolo