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TMS320F28377S: TZCLR for OST Not Working

Lance Hummel
Intellectual 960 points
Part Number: TMS320F28377S


Hi all,

I presently have an interleaved synchronous buck converter I am controlling with my microcontroller.  I also communicate with an external FPGA which provides an outer control loop as well as sends information such as whether or not to turn the converter on or off.  I presently use the ADC PPB and the on chip comparators to produce a DC module output.  That works fine.  For on/off control I read data from the FPGA, look for a certain bit pattern, and based on what the microcontroller reads, send a TZFRC command if the pattern isn't present, or send a TZCLR if it is present.  I'm having issues with the functionality however.  The documentation for configuring the TZFRC response is a little unclear.  All of the OSHT registers look for TZ1-6 as the source, how that correlates to TZFRC and the response is unclear.  When I configure the PWM modules as follows I can never get the OSHT flag to clear

    EALLOW;
    EPwm1Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;
    EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
    EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
    EDIS;

If I forgo this step, the microcontroller is able to clear the register, but the PWM output is still active.  I'm scratching my head as to why I can't clear the OSHT flag in one case and not the other.  Any help would be greatly appreciated.

Lance

  • 0
    TI__Guru 57255 points

    Hi Lance,

    The area of the documentation you are currently in is pretty complex and relatively easy to get mixed up in.  We'll be looking to improve this in the future, but this won't really stop it from being complex :).  The figures are often worth a thousand words here.

    I would recommend to look at two figures extensively:
    [1] Trip Mode Submodule Mode Control Logic   (currently Figure 13-41 in the F2837xS TRM)
    [2] ePWM Trip Input Connectivity (currently Figure 13-49 in the F2837xS TRM)

    Notes:
    1) TZ1-6 are defined in [2] for [1].
    2) Note that in [2] TZ1-3 come from the Input Xbar - furthermore note that the default GPIO set at reset, for each INPUTXBARn is GPIO00
    3) You can see how TZFRC and TZCLR flow into the trip zone submodule in [1]
    4) I would recommend configuring every bitfield from TZCTL, assuming you're using TZCTL2[ETZE] = 0.  The defaults aren't usually what is desired.  For instance if you want OSHT trips to affect ePWMA, TZCTL[TZA] should be configured as you desire, but DCAEVT1/2 should explicitly be configured to 'Do Nothing' (unless there's something special you're trying to do).  [1] and the text around it should help clarify why I'm saying what I am.

    I assume that what is going on in your case is that GPIO00 is still set as the default GPIO for INPUTXBAR1.  This then is forcing TZ1 to trip your PWMs and making it to where your TZFRC/TZCLR are masked.

    Hopefully this helps!


    Thank you,
    Brett