Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE
Tool/software: Code Composer Studio
hello
i used some example and i got PWM1A,PWM2A,PWM1B,&PWM2B.
1.but i did it get isr_ time period ......
2.this is one warning :Description Resource Path Location Type
#10247-D creating output section "IQmathTables" without a SECTIONS ecap_capture_pwm_cpu01 C/C++ Problem
this is my program....
#include "F28x_Project.h"
#include "IQmathLib.h"
#define PWM_Prd 5000;
#define Phi 0;
#pragma DATA_SECTION(sine_table,"IQmathTables");
_iq30 sine_table[512];
void InitEPwm1Example(void);
void InitEPwm2Example(void);
__interrupt void epwm1_isr(void);
void main(void)
{
InitSysCtrl();
InitGpio();
EALLOW;
InitEPwm1Gpio();
InitEPwm2Gpio();
EDIS;
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
EALLOW;
PieVectTable.EPWM1_INT = &epwm1_isr;
GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1;
InitEPwm1Example();
InitEPwm2Example();
EDIS;
IER |= M_INT3;
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
for(;;)
{
asm (" NOP");
}
}
__interrupt void epwm1_isr(void)
{
static unsigned int index = 0;
GpioDataRegs.GPBDAT.bit.GPIO52 = 1;
EPwm1Regs.CMPA.bit.CMPA = EPwm1Regs.TBPRD -
_IQsat(_IQ30mpy((sine_table[index]+_IQ30(0.9999))/2,
EPwm1Regs.TBPRD),EPwm1Regs.TBPRD,0);
if (index++ >511) index = 0;
//EPwm1Regs.ETCLR.bit.INT = 1; // clear ePWM1 interrupt flag
//PieCtrlRegs.PIEACK.all = 4; // ACK for PIE group 3 int
//EPwm1Regs.TBPHS.bit.TBPHS = 0;
EPwm1Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
GpioDataRegs.GPBDAT.bit.GPIO52 = 0;
}
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = PWM_Prd; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm1Regs.TBCTR = 0; // Clear counter
// // Set Compare values0 //
EPwm1Regs.CMPA.bit.CMPA = PWM_Prd; // Set compare A value
EPwm1Regs.CMPB.bit.CMPB = 5000;
// // Setup counter mode //
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
//EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
//EPwm1Regs.TBCTL.bit.SYNCOSEL =TB_CTR_ZERO;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// // Set actions //
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up// count
EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // Clear PWM1A on event A,// down count
EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Set PWM1B on event B, up // count
EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; // Clear PWM1B on event B,// down count
// // Interrupt where we will change the Compare Values //
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = PWM_Prd; // Set timer period 801 TBCLKs
EPwm2Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm2Regs.TBCTR = 0; // Clear counter
// // Set Compare values0 //
EPwm2Regs.CMPA.bit.CMPA = 5000; // Set compare A value
EPwm2Regs.CMPB.bit.CMPB = 2500;
// // Setup counter mode //
// ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
//EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
//EPwm1Regs.TBCTL.bit.SYNCOSEL =TB_CTR_ZERO;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadowing //
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// // Set actions //
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up// count
EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // Clear PWM1A on event A,//down count
EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Set PWM1B on event B, up // count
EPwm2Regs.AQCTLB.bit.ZRO= AQ_SET; // Clear PWM1B on event B,// down count
// // Interrupt where we will change the Compare Values //
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
