CCS/TMS320F28379D: EPWM Time Base Clock Global sync

sasha_kuzya

Part Number: TMS320F28379D

Tool/software: Code Composer Studio

Hello!

I'm develop a dual core project. EPWMs control are separated by different cores. EPWM1-3 is controlled by CPU1 and EPWM1-3 is controlled by CPU2. I'm need to sync Time Base Clock between different cores.

For single core project I'm used TBCLKSYNC register and all working ok:

void pwmSetupSingleCore(void)
{
  EALLOW;
  CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
  EDIS;

  setupPwm1();
  setupPwm2();
  setupPwm3();
  setupPwm4();
  setupPwm5();
  setupPwm6();

  EALLOW;
  CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
  EDIS;
}

But for dual core firmware another solution is needed. In "Table 2-173. PCLKCR0 Register Field Descriptions" (SPRUHM8F) there is information about GTBCLKSYNC field. But there no any examples or any other information abiut of using this feature.

I need an information about GTBCLKSYNC feed. How to sync EPWM Time Base Clock between different cores?

over 7 years ago

0 Kris Parrent over 7 years ago

TI__Genius 15260 points

Hi Sasha,

GTBCLKSYNC is exactly what you are looking for. This is "Global TBCLKSYNC" and works exactly the same way as TBCLKSYNC but across the CPUs.

Regards,
Kris

0 sasha_kuzya over 7 years ago in reply to Kris Parrent

Prodigy 180 points

Hi Kris,

I tryed to change TBCLKSYNC to GTBCLKSYNC but it's not work.

If I use GTBCLKSYNC on each core all ok (not between different cores):

CPU1 Source

CPU2 Source

void pwmSetup(void)
{
	EALLOW;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;

	DevCfgRegs.CPUSEL0.bit.EPWM1 = 1;
	DevCfgRegs.CPUSEL0.bit.EPWM2 = 1;
	DevCfgRegs.CPUSEL0.bit.EPWM3 = 1;
	DevCfgRegs.CPUSEL0.bit.EPWM6 = 1;
	DevCfgRegs.CPUSEL0.bit.EPWM7 = 1;
	DevCfgRegs.CPUSEL0.bit.EPWM8 = 1;
	EDIS;

	pwm9setup();
	pwm10setup();
	pwm11setup();

	EALLOW;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
	EDIS;
}

void pwmSetup(void)
{
	EALLOW;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
	EDIS;

	pwm1setup();
	pwm2setup();
	pwm3setup();
	pwm6setup();
	pwm7setup();
	pwm8setup();

	EALLOW;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
	EDIS;
}

Sync OK:

But if I only change TBCLKSYNC to GTBCLKSYNC:

CPU1 Source

CPU2 Source

void pwmSetup(void)
{
	EALLOW;
	/*CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;*/
	CpuSysRegs.PCLKCR0.bit.GTBCLKSYNC = 0;

	DevCfgRegs.CPUSEL0.bit.EPWM1 = 1;
	DevCfgRegs.CPUSEL0.bit.EPWM2 = 1;
	DevCfgRegs.CPUSEL0.bit.EPWM3 = 1;
	DevCfgRegs.CPUSEL0.bit.EPWM6 = 1;
	DevCfgRegs.CPUSEL0.bit.EPWM7 = 1;
	DevCfgRegs.CPUSEL0.bit.EPWM8 = 1;
	EDIS;

	pwm9setup();
	pwm10setup();
	pwm11setup();

	EALLOW;
	/*CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;*/
	CpuSysRegs.PCLKCR0.bit.GTBCLKSYNC = 1;
	EDIS;
}

void pwmSetup(void)
{
	/*
	EALLOW;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
	EDIS;
	*/

	pwm1setup();
	pwm2setup();
	pwm3setup();
	pwm6setup();
	pwm7setup();
	pwm8setup();

	/*
	EALLOW;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
	EDIS;
	*/
}

It's not working:

May be there is some difference between using TBCLKSYNC and GTBCLKSYNC ?

Note: ePWM1, ePWM2 and ePWM3 - CPU2 ePWMs.

0 Kris Parrent over 7 years ago in reply to sasha_kuzya

TI__Genius 15260 points

Hi Sasha,

I believe you'll want to have a slightly modified flow. The key to this is to make sure that CPU1 does not release GTBCLKSYNC until CPU2 has finished it's PWM configuration (where you would normally release TBCLKSYNC).

So your flow on CPU1 will be something like:

GTBCLKSYNC = 0;

Configure PWMs on CPU1

waitForCpu2ReadySignal();// This and the following step could also be done in an IPC ISR if you didn't want to hang the code to wait for the IPC message from CPU2

GTBCLKSYNC = 1;'

On CPU2 it would just be:

Configure PWMs on CPU2

sendReadySignalToCPU1(); // IPC message to CPU1

Regards,

Kris

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CCS/TMS320F28379D: EPWM Time Base Clock Global sync