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CCS/TMS320F28035: F2803x SPI Communication Issue between DRV8308

Part Number: TMS320F28035
Other Parts Discussed in Thread: DRV8308

Tool/software: Code Composer Studio

Hi, i'm using a card that contains F28035 MCU and DRV8308. I'm using the SPI module with FIFOs and interrupts. DRV8308 chip select state is active high and i can't change it from registers ( tried SPIPRI.STEINV register but didn't work) , so i made the chip select pin output. I'm making it high when transmission starts and making low when RX FIFO has achieved a data. 

My SPI init function goes like this:

	   SpiaRegs.SPICCR.bit.SPISWRESET=0; // Reset SPI

	   SpiaRegs.SPICCR.all=0x0007;       //8-bit character, Loopback mode off
	   SpiaRegs.SPICTL.all=0x0017;       //Interrupt enabled, Master/Slave XMIT enabled
	   SpiaRegs.SPISTS.all=0x0000;
	   SpiaRegs.SPIBRR=0x007F;           // Baud rate
	   SpiaRegs.SPIFFTX.all=0xC023;      // Enable FIFO's, set TX FIFO level to 3
	   SpiaRegs.SPIFFRX.all=0x0023;      // Set RX FIFO level to 3
	   SpiaRegs.SPIFFCT.all=0x00;
	   SpiaRegs.SPIPRI.all=0x0010;

	   SpiaRegs.SPICCR.bit.CLKPOLARITY = 1;
	   SpiaRegs.SPICTL.bit.CLK_PHASE = 0;

	   SpiaRegs.SPICCR.bit.SPISWRESET=1;  // Enable SPI

	   SpiaRegs.SPIFFTX.bit.TXFIFO=0;
	   SpiaRegs.SPIFFRX.bit.RXFIFORESET=1;

What i'm trying to do is writing desired values to DRV8308's registers and reading them back to control if they're OK or not. (total of 13 registers)

For DRV8308 to communicate Reset pin is disabled and Enable pin is enabled. (according to datasheet)

As you can see i'm configuring  FIFOs' register to level 3 and spi registers to 8 bit characters to shift.  I got a timer interrupt that sets data for sending through spi. Then loads it to TXBUF and  sets SpiaRegs.SPIFFTX.bit.TXFIFO to 1.  

Firstly i wanted to ask when i loaded the TXBUF with 3 data interrupt isnt occuring until i'm making TXFIFO 1. Because of that i can't understand how this SPIFFTX and SPIFFRX interrupt level bits works.

Other than that TXFFST is not changing during transmission or after. It always read as zero. Because of that i can't keep track of if the transmission is done or not.

Why TXFFST is not changing while MCU on tranmission ?

After these problems i came up with this idea :

__interrupt void spiTxFifoIsr(void)
{

    DELAY_US(1000);

	count++;
	if(count > 1)
	{
		count=0;
		spi_inf.spiState_u16++;

		spi_inf.getdata_b = TRUE;
		spi_inf.senddata_b = TRUE;
		SpiaRegs.SPIFFTX.bit.TXFIFO = 0;
	}

    SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1;  // Clear Interrupt flag
    PieCtrlRegs.PIEACK.all|=0x20;       // Issue PIE ACK

}

My TxFifoIsr is given above. What i'm doing here is sending TXBUFF two times then setting  TXFIFO to low. So no more TX FIFO interrupt.  But my bool spi_inf.senddata_b will trigger other write or read process ( for any other register) after one is done like that. With this configuration i'm able to write and read values in correct order from DRV8308. 

When i remove if(count>1) condition from code there is not any senseful reading is done. I can't understand this situation.  How it can be corrected ? 


I tried to explain how my code works. For simplicity i'm giving timer interrupt and rx fifo isr codes below:

__interrupt void spiRxFifoIsr(void)
{
    Uint16 i;

    for(i=0;i<3;i++)
    {
        rdata[i]=SpiaRegs.SPIRXBUF;     // Read data
    }


    GpioDataRegs.GPADAT.bit.GPIO19 = 0;

    DELAY_US(100); // Delay after chip select pin low;

    SpiaRegs.SPIFFRX.bit.RXFFOVFCLR=1;  // Clear Overflow flag
    SpiaRegs.SPIFFRX.bit.RXFFINTCLR=1;  // Clear Interrupt flag
    PieCtrlRegs.PIEACK.all|=0x20;       // Issue PIE ack
}

////////////////////////////////////////////////////////////

__interrupt void cpu_timer2_isr(void)
{

	GET_Rxbuffer(&rdata[0]);

	DRV8308_SPI_sendandget_fn();

	PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

Thanks for helping.

  • Rasih,

    I'm sorry that you are having some issues getting this to work. Let's see what's going on.

    It looks like your configuration code will drive the inverted SPISTE. Do you have a scope capture showing this? If you test the code without the DRV chip, is SPISTE driven inverted?

    With the TX FIFO level set to 3, the TXFIFO Interrupt will be triggered when there are less than or equal to 3 words int the FIFO. The opposite goes for the RX FIFO. When the SPIFFRX.RXFFIL = 3, the RX FIFO interrupt will be triggered when there are greater than or equal to 3 words in the FIFO.

    From the look of it, you are never getting to the point where there is more than one word in the FIFO at any given time. The FIFO pointer actually decrements when the word is moved from the TXFIFO into the shift register to be transmitted. As long as there are less than your threshold of 3 words in the TXFIFO, the SPI TX interrupt will keep firing.

    As a test, set your interrupt level to 2 and write 4 words consecutively into the FIFO. you will see that the interrupt will not come until the second word has fully transmitted.

    You are also disabling the TX FIFO inside of the TX FIFO ISR. this might be an issue because the FIFO may be turned off during a transmission. Instead of setting TXFIFO to 0, set TXFFIENA to 0 to disable the interrupt and not the FIFO itself. in your timer interrupt, you can set TXFFIENA to 1 to enable the interrupt.

    Really here it looks like you might just be having some confusion of the synchronization between the three interrupts. You might be able to simplify the configuration by eliminating the TXFIFO interrupt. You can rely on the RXFIFO interrupt count to determine when to read and how many words have completed transmitting.

    I hope this helps get you going again.

    Regards,
    Mark
  • Hi Mark,

    Thanks for prompt feedback. You asked about SPISTE pin condition. I should be more specific about it. I'm configuring SPIASTE pinmux to normal GPIO pin. Before i load the TXBUF setting it high and when RX interrupt occurs setting it low by hand to complete transmission.

    You're right probably i was interrupting fifo when i was doing TXFIFO to 0. I set TXFFIENA to 0 at initialization. Then , just after i load TXBUF setting TXFFIENA to 1 and interrupt occurs for TXFIFO. Now i dont have any issue about writing and reading from DRV8308.

    I really appreciate it. Thanks a lot.
  • I am happy to help.

    Please don't hesitate to post again in the future if you have any other questions.