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TMS320F28069M: PWM programming for Three Phase Motor bridges

user4957458
Expert 1065 points
Part Number: TMS320F28069M
Other Parts Discussed in Thread: CONTROLSUITE

Dear All

I did not tested the code below yet. 

Can anyone say if it will work? Notice two cases

Can you detect any error, please?

Active High, Complementary Outputs, Upcount, PWM4,5,6, to generate 3 phase sines

********************************************************************

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;

EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;


EPwm4Regs.TBPRD = 4500; // Set timer period
EPwm4Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm4Regs.TBCTR = 0x0000; // Clear counter

//
// Setup TBCLK
//
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading

EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;


EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;;

EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

//
// Setup compare
//
EPwm4Regs.CMPA.half.CMPA = 0;

//
// Set actions
//

EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm4Regs.AQCTLB.bit.ZRO = AQ_CLEAR;
EPwm4Regs.AQCTLB.bit.CAU = AQ_SET;


//
// Active Complementary HIGH PWMs - Setup Deadband
//
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm4Regs.DBRED = 90;
EPwm4Regs.DBFED = 90;


EPwm5Regs.TBPRD = 4500; // Set timer period
EPwm5Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm5Regs.TBCTR = 0x0000; // Clear counter

//
// Setup TBCLK
//
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading

EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;

EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

//
// Setup compare
//
EPwm5Regs.CMPA.half.CMPA = 0;

//
// Set actions
//
EPwm5Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm5Regs.AQCTLB.bit.ZRO = AQ_CLEAR;
EPwm5Regs.AQCTLB.bit.CAU = AQ_SET;


//
// Active HIGH PWMs - Setup Deadband
//
EPwm5Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm5Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm5Regs.DBRED = 90;
EPwm5Regs.DBFED = 90;

EPwm6Regs.TBPRD = 4500; // Set timer period
EPwm6Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm6Regs.TBCTR = 0x0000; // Clear counter

//
// Setup TBCLK
//
EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading

EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW;

EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm6Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

//
// Setup compare
//
EPwm6Regs.CMPA.half.CMPA = 0;

//
// Set actions
//

EPwm6Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm6Regs.AQCTLA.bit.ZRO = AQ_CLEAR;
EPwm6Regs.AQCTLA.bit.CAU = AQ_SET;


//
// Active HIGH PWMs - Setup Deadband
//
EPwm6Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm6Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm6Regs.DBRED = 90;
EPwm6Regs.DBFED = 90;

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

************************************************************

Active High, Independent Outputs, Upcount, PWM4,5,6, to generate a ramp between two phases

*********************************************************************

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

EPwm4Regs.TBPRD = 4500; // Period = 4500 TBCLK counts
EPwm4Regs.CMPA.half.CMPA = 0; // Compare A = 0 TBCLK counts
EPwm4Regs.CMPB = 0; // Compare B = 0 TBCLK counts
EPwm4Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm4Regs.TBCTR = 0; // clear TB counter
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled
EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero
EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET;
EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR;
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;

EPwm5Regs.TBPRD = 4500; // Period = 4500 TBCLK counts
EPwm5Regs.CMPA.half.CMPA = 0; // Compare A = 0 TBCLK counts
EPwm5Regs.CMPB = 0; // Compare B = 0 TBCLK counts
EPwm5Regs.TBPHS.half.TBPHS = 0x0000;
EPwm5Regs.TBCTR = 0; // clear TB counter
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm5Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled
EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK
EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero
EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero
EPwm5Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm5Regs.AQCTLB.bit.ZRO = AQ_SET;
EPwm5Regs.AQCTLB.bit.CBU = AQ_CLEAR;
EPwm5Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;


EPwm6Regs.TBPRD = 4500; // Period = 4500 TBCLK counts
EPwm6Regs.CMPA.half.CMPA = 0; // Compare A = 0 TBCLK counts
EPwm6Regs.CMPB = 0; // Compare B = 0 TBCLK counts
EPwm6Regs.TBPHS.half.TBPHS = 0x0000;
EPwm6Regs.TBCTR = 0; // clear TB counter
EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm6Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled
EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK
EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero
EPwm6Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero
EPwm6Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm6Regs.AQCTLB.bit.ZRO = AQ_SET;
EPwm6Regs.AQCTLB.bit.CBU = AQ_CLEAR;
EPwm6Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;

EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

*****************************************************************

Thanks

Luis Gonçalves

  • 0
    TI__Genius 15935 points
    Hi Luis,

    Is this code coming from C2000 example? What is the error you found during the building process? Thanks.

    Best regards,
    Chen
  • 0 in reply to Chen Jiang ti
    Expert 1065 points
    Dear Chen

    The code is compiling Ok. I only want if I have any conceptual error or other to not have surprises in the experimenting. And in the field it is very difficult to correct the errors and it can take time. If someone with experience can help me. This is only the configuration of the PWMs.

    Thanks

    Luis Gonçalves
  • 0 in reply to user4957458
    TI__Guru** 116170 points
    You can refer to the example project in controlSUITE, there are many 3 phase motor control example projects for your reference which includes pwm configuration for 3-phase bridge as below. The pwm configuration can be used on F2806x also without any change, only need to change the epwm1/2/3 to epwm4/5/6, and change the count mode if you want to up count mode, not up/down count mode.

    \controlSUITE\development_kits\HVMotorCtrl+PfcKit_v2.1\HVPM_Sensorless_2833x