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TMS320F28062: FIFO interrupt

Seven Han
Intellectual 600 points
Part Number: TMS320F28062


Hi，

Is it reliable to use 1M baud rate to fill the data sent by FIFO in the FIFO receiver interrupt of  SPI? Using 4 stage FIFO transceiver data.

I measured FIFO interruption time consuming 3 microseconds, 1M baud rate is 1 microseconds a clock,Is the clock missing in the first 2 microseconds resulting in sending erroneous data?

  • 0
    Guru 30330 points
    Hello Seven,

    I am not sure if I understand your question. Did you measure the total time it took to service the RXFIFO ISR? and you are worried that the SPI FIFO will not be able to keep up? If so, please read my explanation below.

    The short answer is yes, the SPI FIFO will have no problem keeping up with a 1MHz baud rate. If configured properly, the RX FIFO will trigger an interrupt after 4 words have been received. It will not interrupt every clock cycle.

    For a longer answer, I am going to make some assumptions here. please correct me if I am wrong. Regardless of the values chosen, the concept will hopefully make things clear.

    SPI- 1 MHz clock rate
    RXFIFO Interrupt level - 4 words (the maximum)
    SPI Word length - 16 bits

    Assuming that there is continuous data being transmitted (no breaks between 16 bit words) the following timings will be true:
    - 1MHz clock rate is 1us cycle time or 1us per bit
    - 4 x 16 bit words = 64 bits
    - total time to fill the FIFO is 64us

    If you measure the duration of of your RX FIFO ISR to be 3us, you have PLENTY of time to handle a saturated SPI bus at 1MHz, assuming that the rest of your system allows for 3us of SPI handling per 64us block.

    Thanks,
    Mark