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TMS320F28035: How to select common ISR while using ePwm3,4 for one full bridge and epwm5 for buck converter and adc soc selection?

Pushpender
Prodigy 80 points
Part Number: TMS320F28035


Hello

i am driving buck converter with epwm 5A(up mode) at 50KHz using 3p3z compensation and one full bridge with (up down mode)epwm3A,3B and 4A,4B. Full brdige pwm freq changed to 10KHz and 20KHz depending on some condition. Duty cycle for epwm5 is updated in 50KHz pwm period interrupt and epwm3,4 in 10/20KHz pwm period interrupt. ADC SOC configured to use epwm5 CTR_ZERO first event for all adc channels.

My application has 4 ISR:  XINT1, epwm3 period, epwm5 period, timer2 int(1KHz)

 

I need to know following things:

1.) How to decide common ISR for these pwm's proper functionality or to use adc interrupt to update their duty cycle.

2.) How to choose ADC SOC for channels used by buck converter and full bridge for feedback and input readings.

3.) Best approach to use pwm priority when multiple pwm interrupt enabled, when it is desired that epwm5 interrupt has higher priority so that it can be served while serving epwm3 period isr and how to implement it.

thanks

pushpender

  • 0
    TI__Genius 10820 points

    Hi Pushpender,

    1.) How to decide common ISR for these pwm's proper functionality or to use adc interrupt to update their duty cycle.

    HN: If you want a single ISR for all these tasks, the simple rule is to use the ISR that is triggered at the highest rate as the single ISR (master). All other functions running at a slower rate can be time multiplexed inside this ISR. This is fairly straight-forward to implement if the rates at which these separate tasks are run are integral multiples of the master ISR rate.

    2.) How to choose ADC SOC for channels used by buck converter and full bridge for feedback and input readings.

    HN: Please refer to example solutions for the buck converter www.ti.com/.../BOOSTXL-BUCKCONV and for the full-bridge

    .

    3.) Best approach to use pwm priority when multiple pwm interrupt enabled, when it is desired that epwm5 interrupt has higher priority so that it can be served while serving epwm3 period isr and how to implement it.

    HN: This post should help  

    I hope this helps.

    Hrishi