TMS320F28377D: TMS320F28377D ECap Synchronization

Daniel Kakaley

Part Number: TMS320F28377D
Other Parts Discussed in Thread: C2000WARE

I would like to synchronize the ECAP1 - ECAP6 Clocks on the TMS320F28377D processor. I am measuring phase differences between ECAP1 and other ECAPs, and I think that I am seeing phase differences between ECAPs that do not seem to correspond to physical phase differences. I have yet to confirm that this is the case.

Anyways, I would like to synchronize all ECAP TSCTR Counter Clocks and I'm trying to figure out the best way to do so.

1) I would like to monitor the phase difference between ECAP TSCTR Clocks so as to confirm if the phase between ECAPs is changing.

Would this be measured by reading the following registers:

/* Read and store each TSCTR Register */
Ecap1_Counter = ECap1Regs.TSCTR;
Ecap2_Counter = ECap2Regs.TSCTR;
Ecap3_Counter = ECap3Regs.TSCTR;
Ecap4_Counter = ECap4Regs.TSCTR;
Ecap5_Counter = ECap5Regs.TSCTR;
Ecap6_Counter = ECap6Regs.TSCTR;

/* Calculate TSCTR Deltas */
ECap12_Delta  = Ecap1_Counter - Ecap2_Counter;
ECap13_Delta  = Ecap1_Counter - Ecap3_Counter;
ECap14_Delta  = Ecap1_Counter - Ecap4_Counter;
ECap15_Delta  = Ecap1_Counter - Ecap5_Counter;
ECap16_Delta  = Ecap1_Counter - Ecap6_Counter;

It is my understanding that these "Delta" calculations should stay at least constant if all ECAPs are synchronized. There should be a steady state offset in these readings because reading these counters takes clock cycles. Is this a correct way to quantify the synchronization of all the ECAPs?

2) I would like to software synchronize the ECAPs.

On initialization, I need to set the following Registers;

/* Set up ECAPs 1 - 6 for SWSYNC Input */
EALLOW;
ECap1Regs.ECCTL2.SYNCO_SEL.bit = 0U;
ECap2Regs.ECCTL2.SYNCO_SEL.bit = 0U;
ECap3Regs.ECCTL2.SYNCO_SEL.bit = 0U;
ECap4Regs.ECCTL2.SYNCO_SEL.bit = 0U;
ECap5Regs.ECCTL2.SYNCO_SEL.bit = 0U;
ECap6Regs.ECCTL2.SYNCO_SEL.bit = 0U;

/* Enable SYNC Input on ECAP 1 */
ECap1Regs.ECCTL2.SYNCI_EN.bit  = 1U;
EDIS;

When I need to synchronize, I need to trigger a SWSYNC event.

/* Synchronize all ECAPs */
EALLOW;
ECap1Regs.ECCTL2.SWSYNC = 1U;
EDIS;

So my questions are:
- Will this work to synchronize the TSCTR clocks between all the ECAPs? Are there other registers that I need to set.
- Will this synchronize the TSCTR counters with zero delay? i.e. Phase difference is zero between counters. If not, is there a value I can insert into the CTRPHS Register to account for the delay?

over 7 years ago

0 Nirav Ginwala over 7 years ago

TI__Genius 15385 points

Hi Daniel,

Answers to all your questions is "Yes", your configuration looks to be correct, and you should be able to synchronize through SWSYNC. All your configurations looks to be correct, can you share your results or delta between the counters that you are seeing? Also, are you in debug mode? One other suggestion is to use CTRPHS register to configure different values for each eCAP so that you can see similar delta when you read, that should confirm synchronization.

Regards,
Nirav

0 Daniel Kakaley over 7 years ago in reply to Nirav Ginwala

Prodigy 225 points

So I have gotten SWSYNC working, however, it wasn't the code I have above.

Basically, I want to sync all the counters on startup, because when I compared TSCTR between ECAPs I was seeing unpredictable variation.

So on startup (in addition to all my other ECAP initialization), I do the following:

ECap1Regs.ECCTL2.bit.SYNCI_EN = 1;   /* Enable sync in*/
ECap1Regs.ECCTL2.bit.SYNCO_SEL = 0;  /* Pass through*/  

ECap2Regs.ECCTL2.bit.SYNCI_EN = 1;   /* Enable sync in*/
ECap2Regs.ECCTL2.bit.SYNCO_SEL = 0;  /* Pass through*/   

ECap3Regs.ECCTL2.bit.SYNCI_EN = 1;   /* Enable sync in*/
ECap3Regs.ECCTL2.bit.SYNCO_SEL = 0;  /* Pass through*/

ECap4Regs.ECCTL2.bit.SYNCI_EN = 1;   /* Enable sync in*/
ECap4Regs.ECCTL2.bit.SYNCO_SEL = 0;  /* Pass through*/ 

ECap5Regs.ECCTL2.bit.SYNCI_EN = 1;   /* Enable sync in*/
ECap5Regs.ECCTL2.bit.SYNCO_SEL = 0;  /* Pass through*/     

ECap6Regs.ECCTL2.bit.SYNCI_EN = 1;   /* Enable sync in*/
ECap6Regs.ECCTL2.bit.SYNCO_SEL = 0;  /* Pass through*/  

//Set up ECAP1 and ECAP4 for External Sync
EALLOW;
InputXbarRegs.INPUT5SELECT = 102U; //0x102
GpioDataRegs.GPDDAT.bit.GPIO102 = 0;
SyncSocRegs.SYNCSELECT.bit.ECAP1SYNCIN = 5U; //0x101
SyncSocRegs.SYNCSELECT.bit.ECAP4SYNCIN = 5U; //0x101
EDIS;

//Synchronize ECAPS 1 through 6
ECap1Regs.ECCTL2.bit.SWSYNC = 1;
ECap4Regs.ECCTL2.bit.SWSYNC = 1;

This essentially follows Section 16.5.6 of the Technical Reference Manual for the F28377D. Some changes that I made are detailed below. Basically I selected GPIO102 as my unused GPIO, and instead of programming 0x101 to the ECAP1SYNCIN and ECAP4SYNCIN Registers, I programmed 5U to it (these are three bit registers).

To use SWYNC with ECAP1 and ECAP4, the following workaround can be implemented:

• Select an unused GPIO in InputXbarRegs.INPUT5SELECT.

• Configure this GPIO in output mode and Write ‘0’ to GPIO DAT register. By default this is programmed to GPIO0 so any activity on this pin will cause problems with the SWSYNC

• Program SYNCSEL[ECAPxSYNCIN] = 5U0x101. This will take ECAPx.EXTSYNCIN to an inactive state.

The Results that I am seeing on this are from taking differences between each ECAPs TSCTR.

Between ECAP1 and ECAP2: 4 clock counts
Between ECAP1 and ECAP3: 10 clock counts
Between ECAP1 and ECAP4: 10 clock counts
Between ECAP1 and ECAP5: 14 clock counts
Between ECAP1 and ECAP6: 19 clock counts

I don't actually know how much of the deltas are from the delay in reading ECap1Regs.TSCTR vs ECap2Regs.TSCTR, etc. and how much is error in the SWSYNC method of synchronization, but I am getting them pretty close and this is consistent every time that I run this code. If I remove other statements from the code, I get weird things such as:

ECAP1-3 and ECAP4-6 are are synced in their groups but the two groups are not synced with each other
ECAP4-6 are sometimes synced and other times not synced.

0 Nirav Ginwala over 7 years ago in reply to Daniel Kakaley

TI__Genius 15385 points

Hi Daniel,

Couple of configuration that looks incorrect if you are trying to sync all the ECAPs i.e. ECAP1 to ECAP6.

SyncSocRegs.SYNCSELECT.bit.ECAP4SYNCIN = 4U; // This will sync on the sync signal coming from ECAP1

Remove below line from your code:
ECap4Regs.ECCTL2.bit.SWSYNC = 1; -- Not needed since any source of Sync for ECAP1 will pass through ECAP4

Also, one more important thing to note, since you are reading TSCTR registers sequentially, there will be delay between each reads, and that will vary based on the compiler, again there is no delay in ECAP, they are all synced in the same cycle, but since you read them one at a time the counter is still running so you will see the delta.

Now if you want to verify if there is any delay in sync between each ECAP best way to capture that is using CAPx registers. For that you will have to trigger an event through GPIO via INPUTXBAR, which will be same for all eCAPs, also configure the polarity, put it in Single shot mode, enable Capture mode and then read the CAPx registers they all should have the same count value. You can find the example code in C2000Ware.

Regards,
Nirav

0 Daniel Kakaley over 7 years ago in reply to Nirav Ginwala

Prodigy 225 points

So I adjusted to your suggested code, and I see the following:

Between ECAP1 and ECAP2: 4 clock counts
Between ECAP1 and ECAP3: 10 clock counts
Between ECAP1 and ECAP4: 16 clock counts
Between ECAP1 and ECAP5: 21 clock counts
Between ECAP1 and ECAP6: 26 clock counts

I know my software method of determining the deltas has inherent delay (and that your hardware method of verifying it is better). I am not concerned if there is delay (as long as it is synchronized and repeatable and close to zero i.e. <30 clock cycles). It is definitely working, thanks!

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TMS320F28377D: TMS320F28377D ECap Synchronization