TMS320F28069: Ramp Generator in Comparator Subsystem: less slope?

StephanS

Part Number: TMS320F28069

Hi,

we try to implement peak current control with compensation ramp and are using the ramp generator in the CMPSS comparator subsystem.

Datasheet says the reference 12-bit DAC uses the most significant 12 bits of the RAMPSTS countdown register as its input. The low 4 bits of the RAMPSTS countdown register effectively act as a prescale for the falling-ramp rate configurable with RAMPDECVALA.

The problem is that even with the lowest RAMPDECVAL of 1 and the fix prescale of 4 bits, the slope (decrement) is too big.
The RAMPSTS is decremented at SYSCLK, so no chance to reduce the slope further, right?

Any help is appreciated.

Stephan

over 7 years ago

0 StephanS over 7 years ago

Genius 4066 points

Correction: the 28069 only has a 10-bit DAC while newer devices like 28075 or 280049 have 12 bit, but the principle is the same: we cannot get the slope small enough.

0 Frank Ankapong over 7 years ago in reply to StephanS

TI__Mastermind 28275 points

Hi Stephan,

Can you clarify what you are looking for? Do you want a steep slope (DAC decrements faster) or a shallow slope (DAC decrements slower)?

0 StephanS over 7 years ago in reply to Frank Ankapong

Genius 4066 points

Hi Frank,
we are looking for a shallow slope.

0 Frank Ankapong over 7 years ago in reply to StephanS

TI__Mastermind 28275 points

Stephan,

Ok, got it. Definitely an interesting case. On the 28069, the maximum "prescale" is effectively 64. Without reducing the system clock, I'm not aware of any way to get a shallower slope.

0 StephanS over 7 years ago in reply to Frank Ankapong

Genius 4066 points

Frank,

thanks for confirmation, so nothing missed here.
Although it won't help for now, mabe this could be considered on newer devices...
Plus having a decrement OR increment in the slope to be more flexible.

Stephan

0 Frank Ankapong over 7 years ago in reply to StephanS

TI__Mastermind 28275 points

Stephan,

Our newer devices actually have steeper slopes than the 28069 if you take into account their 12-bit COMPDAC and faster system clock. However to mitigate this, you can load the COMPDAC on PWMSYNC (EPWM has much bigger prescale). Though not quite the same as decrementing with RAMPGEN, it's at least an option. This feature is not available on the 28069 but we can consider your request for future enhancements.

0 tlee over 7 years ago in reply to Frank Ankapong

TI__Guru 62975 points

Stephan,

Two more non-ideal options that may help some:

Phase-shift the ramp generator PWMSYNC signal so that the ramp does not begin to decrement until further into the control cycle
Generate multiple PWMSYNC signals per control cycle and update the RAMPMAXREF value as needed to create a saw-tooth decrement ramp

-Tommy

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F28069: Ramp Generator in Comparator Subsystem: less slope?