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TMS320F28035: ILPFCkit PWM SOC question.

Howard Zou
Genius 12365 points

Part Number: TMS320F28035

Hi, in the ILPFC project's main function, there are codes below:

EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable ePWM1 SOCA pulse
EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; // SOCA from ePWM1 Zero event
EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST; // Trigger ePWM1 SOCA on every event
EPwm1Regs.ETSEL.bit.SOCBEN = 1; // Enable ePWM1 SOCB pulse
EPwm1Regs.ETSEL.bit.SOCBSEL = ET_CTR_PRD; // SOCB from ePWM1 PRD event
EPwm1Regs.ETPS.bit.SOCBPRD = ET_1ST; // Trigger ePWM1 SOCB on every event

EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable ePWM2 SOCA pulse
EPwm2Regs.ETSEL.bit.SOCASEL = ET_CTRU_CMPA; // SOCA from ePWM2 CMPA up event
EPwm2Regs.ETPS.bit.SOCAPRD = ET_1ST; // Trigger ePWM2 SOCA on every event
EPwm2Regs.ETSEL.bit.SOCBEN = 1; // Enable ePWM2 SOCB pulse
EPwm2Regs.ETSEL.bit.SOCBSEL = ET_CTRD_CMPA; // SOCB from ePWM2 CMPA down event
EPwm2Regs.ETPS.bit.SOCBPRD = ET_1ST; // Trigger ePWM2 SOCB on every event

// Configure ePWMs to generate ADC SOC pulses
EPwm3Regs.ETSEL.bit.SOCAEN = 1; // Enable ePWM3 SOCA pulse
EPwm3Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; // SOCA from ePWM3 zero event
EPwm3Regs.ETPS.bit.SOCAPRD = ET_1ST; // Trigger ePWM3 SOCA on every event
EPwm3Regs.ETSEL.bit.SOCBEN = 1; // Enable ePWM3 SOCB pulse
EPwm3Regs.ETSEL.bit.SOCBSEL = ET_CTRU_CMPB; // SOCB from ePWM3 CMPB up event
EPwm3Regs.ETPS.bit.SOCBPRD = ET_1ST; // Trigger ePWM3 SOCB on every event

EPwm4Regs.ETSEL.bit.SOCAEN = 1; // Enable ePWM4 SOCA pulse
EPwm4Regs.ETSEL.bit.SOCASEL = ET_CTRU_CMPA; // SOCA from ePWM4 CMPA up event
EPwm4Regs.ETPS.bit.SOCAPRD = ET_1ST; // Trigger ePWM4 SOCA on every event
EPwm4Regs.ETSEL.bit.SOCBEN = 1; // Enable ePWM4 SOCB pulse
EPwm4Regs.ETSEL.bit.SOCBSEL = ET_CTRU_CMPB; // SOCB from ePWM4 CMPB up event
EPwm4Regs.ETPS.bit.SOCBPRD = ET_1ST; // Trigger ePWM4 SOCB on every event

epwm1SOCA is triggered every time epwm1 counter=period, so Ipfc, VL, VN, Vbus will be sampled twice between one ISR. But the picture below shows that they will only be sampled once. The picture below is resonable since it's not resonable to sample VL, VN, Vbus twice, because only one result is dealt with in ISR. But where is the problem for the code above?


  • 0
    TI__Genius 16085 points
    Hi Howard,

    1. epwm1SOCA is triggered every time epwm1 counter=period, so Ipfc, VL, VN, Vbus will be sampled twice between one ISR.

    Yes, Ipfc will be over-sampled 8 times within 1 ISR period in total. VL, VN, Vbus will be sampled twice within 1 ISR period. However, only one (VL, VN, Vbus) sample will be used because ISR frequency is half of the PWM1 frequency.

    2.But the picture below shows that they will only be sampled once. The picture below is resonable since it's not resonable to sample VL, VN, Vbus twice, because only one result is dealt with in ISR. But where is the problem for the code above?

    Yes, you are right. The picture is not accurate enough. I think the picture is to show that only one group of (VL, VN, Vbus) are utilized within one ISR cycle.


    Best regards,
    Chen
  • 0 in reply to Chen Jiang ti
    TI__Genius 12365 points
    Hi, there is code below in "ILPFC_Base-Settings.h". I suppose it's to convert the number to Q24 format, but why we are multiplying 4095, not 4096?
    #define VBUS_OVP_THRSHLD ((int32)((435.0/VBUS_MAX_SENSE)*4095*4095))
  • 0 in reply to Chen Jiang ti
    TI__Genius 12365 points
    In ILPFC-DPL-ISR.asm, for voltage and current loop control(INCR_BUILD = 3) the software flow can be concluded as:
    read ADC result --> PFC ICMD --> CNTL_2P2Z current control --> PWM1 register update --> calculate 1/(Vrms*Vrms)--> calculate average Vbus --> CNTL_2P2Z voltage control --> calculate Vrect.
    The sequence seems unreasonable, because we have to first implement CNTL_2P2Z voltage control and get the output, and then we can implement the CNTL_2P2Z current control . And we have to calculate Vrect before CNTL_2P2Z voltage control.
  • 0 in reply to Chen Jiang ti
    TI__Genius 12365 points
    For sine analyzer, why don't we set Threshold=0, what's the benefit of such a threshold?
    //sine analyzer initialization
    sine_mainsV.Vin=0;
    sine_mainsV.Iin=0;
    sine_mainsV.SampleFreq=_IQ15(10000.0);
    sine_mainsV.Threshold=_IQ15(0.1);//(0.015);//(0.02);