Tool/software: TI C/C++ Compiler
Hi, I have an unpleasant error.
Yes, it very specific problem, but...
In some mode, I have damage my data in RAM. It is random damage.
And I cannot find where I do it! I have a lot of interrupts, it is big project, but previous project was based on the same program and I was not any problems.
I am using --opt_level = 4; --opt_for_speed = 5.
There is my memory link (for F2808):
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
RAML0_1 : origin = 0x008000, length = 0x002000 /* on-chip RAM block L0+L1 !@ pve 18.10.17 @! */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHD : origin = 0x3E8000, length = 0x004000 /* on-chip FLASH */
FLASHC : origin = 0x3EC000, length = 0x004000 /* on-chip FLASH */
FLASHA : origin = 0x3F4000, length = 0x003F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
ROM : origin = 0x3FF000, length = 0x000FC0 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
RAMM0 : origin = 0x000000, length = 0x000400 /* on-chip RAM block M0 */
BOOT_RSVD : origin = 0x000400, length = 0x000080 /* Part of M1, BOOT rom will use this for stack */
RAMM1 : origin = 0x000480, length = 0x000380 /* on-chip RAM block M1 */
RAMH0 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block H0 (first part - for data) - copy to data space !@ pve 18.10.16 @! */
RAMH0_F : origin = 0x00B000, length = 0x001000 /* on-chip RAM block H0 (second part - for filter) - copy to data space !@ pve 18.10.16 @! */
FLASHB : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHD,
RUN = RAML0_1,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0 PAGE = 1
.ebss : > RAMH0 PAGE = 1
.esysmem : > RAMH0 PAGE = 1
firldb1 align(0x100) > RAMH0_F, PAGE = 1
firldb2 align(0x100) > RAMH0_F, PAGE = 1
firldb3 align(0x100) > RAMH0_F, PAGE = 1
firldb4 align(0x100) > RAMH0_F, PAGE = 1
firldb5 align(0x100) > RAMH0_F, PAGE = 1
firldb6 align(0x100) > RAMH0_F, PAGE = 1
firldb7 align(0x100) > RAMH0_F, PAGE = 1
firldb8 align(0x100) > RAMH0_F, PAGE = 1
firldb9 align(0x100) > RAMH0_F, PAGE = 1
firldb10 align(0x100) > RAMH0_F, PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHC PAGE = 0 /* Math Code, FLASHC - original location */
IQmathTables : > ROM PAGE = 0, TYPE = NOLOAD /* Math Tables In ROM */
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
}
Is it correct link? Or I have some mistakes?
And how I can debug this problem (because this happens only on a real device in working operation)
MEMORY{PAGE 0: /* Program Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
RAML0_1 : origin = 0x008000, length = 0x002000 /* on-chip RAM block L0+L1 !@ pve 18.10.17 @! */ OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */ FLASHD : origin = 0x3E8000, length = 0x004000 /* on-chip FLASH */ FLASHC : origin = 0x3EC000, length = 0x004000 /* on-chip FLASH */ FLASHA : origin = 0x3F4000, length = 0x003F80 /* on-chip FLASH */ CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ ROM : origin = 0x3FF000, length = 0x000FC0 /* Boot ROM */ RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ /* Registers remain on PAGE1 */
RAMM0 : origin = 0x000000, length = 0x000400 /* on-chip RAM block M0 */ BOOT_RSVD : origin = 0x000400, length = 0x000080 /* Part of M1, BOOT rom will use this for stack */ RAMM1 : origin = 0x000480, length = 0x000380 /* on-chip RAM block M1 */// RAML1 : origin = 0x009600, length = 0x000A00 /* on-chip RAM block L1 - changed: from 9000 to 9600, from 1000 to A00 !@ pve 18.10.17 @! */ RAMH0 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block H0 (first part - for data) - copy to data space !@ pve 18.10.16 @! */ RAMH0_F : origin = 0x00B000, length = 0x001000 /* on-chip RAM block H0 (second part - for filter) - copy to data space !@ pve 18.10.16 @! */ FLASHB : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */// RAMH0 : origin = 0x3FA000, length = 0x002000 /* on-chip RAM block H0 */}
/* Allocate sections to memory blocks. Note: codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code execution when booting to flash ramfuncs user defined section to store functions that will be copied from Flash into RAM*/ SECTIONS{ /* Allocate program areas: */ .cinit : > FLASHA PAGE = 0 .pinit : > FLASHA, PAGE = 0 .text : > FLASHA PAGE = 0 codestart : > BEGIN PAGE = 0 ramfuncs : LOAD = FLASHD, RUN = RAML0_1, LOAD_START(_RamfuncsLoadStart), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0 csm_rsvd : > CSM_RSVD PAGE = 0 /* Allocate uninitalized data sections: */ .stack : > RAMM0 PAGE = 1// .ebss : > RAML1 PAGE = 1 .ebss : > RAMH0 PAGE = 1 .esysmem : > RAMH0 PAGE = 1
firldb1 align(0x100) > RAMH0_F, PAGE = 1 firldb2 align(0x100) > RAMH0_F, PAGE = 1 firldb3 align(0x100) > RAMH0_F, PAGE = 1 firldb4 align(0x100) > RAMH0_F, PAGE = 1 firldb5 align(0x100) > RAMH0_F, PAGE = 1 firldb6 align(0x100) > RAMH0_F, PAGE = 1 firldb7 align(0x100) > RAMH0_F, PAGE = 1 firldb8 align(0x100) > RAMH0_F, PAGE = 1 firldb9 align(0x100) > RAMH0_F, PAGE = 1 firldb10 align(0x100) > RAMH0_F, PAGE = 1
/* Initalized sections go in Flash */ /* For SDFlash to program these, they must be allocated to page 0 */ .econst : > FLASHA PAGE = 0 .switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */ IQmath : > FLASHC PAGE = 0 /* Math Code, FLASHC - original location */ IQmathTables : > ROM PAGE = 0, TYPE = NOLOAD /* Math Tables In ROM */
/* .reset is a standard section used by the compiler. It contains the */ /* the address of the start of _c_int00 for C Code. /* /* When using the boot ROM this section and the CPU vector */ /* table is not needed. Thus the default type is set here to */ /* DSECT */ .reset : > RESET, PAGE = 0, TYPE = DSECT vectors : > VECTORS PAGE = 0, TYPE = DSECT
}
