LAUNCHXL-F28069M: I2C Communication Issue in Motorware.

Update: I've updated managed to get output back on the i2C lines. Here is my updated code:

void accel_Write(HAL_Handle halHandle, uint16_t register_add, uint16_t data ){
//    I2C_enable(halHandle->i2cHandle);
//
    while(I2C_isMasterBusy(halHandle->i2cHandle));
    I2C_clearStopConditionDetection(halHandle->i2cHandle);
    while(I2C_isMasterStopBitSet(halHandle->i2cHandle));


//    while(!((I2C_getStatus(halHandle->i2cHandle) & (I2C_I2CSTR_XRDY_BITS | I2C_I2CSTR_ARDY_BITS))));
//    // If a NACK occurred, SCL is held low and STP bit cleared
//    if ( I2C_isNoAck(halHandle->i2cHandle) )
//    {
//        I2C_setMasterStopBit(halHandle->i2cHandle);  // send STP to end transfer
//        I2C_clearNoAckBit(halHandle->i2cHandle);     // clear NACK bit
//    }
    //I2C_disable(halHandle->i2cHandle);
    I2C_MasterControl(halHandle->i2cHandle, I2C_Control_Single_TX, 0, 2);


    while(!((I2C_getStatus(halHandle->i2cHandle) & (I2C_I2CSTR_XRDY_BITS | I2C_I2CSTR_ARDY_BITS))));
    // If a NACK occurred, SCL is held low and STP bit cleared
    if ( I2C_isNoAck(halHandle->i2cHandle) )
    {
        I2C_setMasterStopBit(halHandle->i2cHandle);  // send STP to end transfer
        I2C_clearNoAckBit(halHandle->i2cHandle);     // clear NACK bit
        return;
    }
    I2C_putData(halHandle->i2cHandle, register_add);

    while(!((I2C_getStatus(halHandle->i2cHandle) & (I2C_I2CSTR_XRDY_BITS | I2C_I2CSTR_ARDY_BITS))));
    // If a NACK occurred, SCL is held low and STP bit cleared
    if ( I2C_isNoAck(halHandle->i2cHandle) )
    {
        I2C_setMasterStopBit(halHandle->i2cHandle);  // send STP to end transfer
        I2C_clearNoAckBit(halHandle->i2cHandle);     // clear NACK bit
        return;
    }
    I2C_putData(halHandle->i2cHandle, data);

    while(!((I2C_getStatus(halHandle->i2cHandle) & (I2C_I2CSTR_XRDY_BITS | I2C_I2CSTR_ARDY_BITS))));
    // If a NACK occurred, SCL is held low and STP bit cleared
    if ( I2C_isNoAck(halHandle->i2cHandle) )
    {
        I2C_setMasterStopBit(halHandle->i2cHandle);  // send STP to end transfer
        I2C_clearNoAckBit(halHandle->i2cHandle);     // clear NACK bit
        return;
    }

    I2C_setMasterStopBit(halHandle->i2cHandle);

    while(!I2C_isStopConditionDetected(halHandle->i2cHandle));
} // end of accel_Write() function

There is a screen shot of my output below. Oddly, most of the time I am getting the result on the left. It is almost correct, but all of the bits seem to be shifted to the right by one. I believe the cause is because of the oddly short start condition hold time. I have no idea how to manipulate that. 

On the right is what I would like to see. The first "diamond" represents the longer start condition, and the last two represent the "Ack" and the Stop bit. 

With the code updated as is above, most of the data frames appear as on the left, with the odd frame here and there being correct. 

If I comment out the top 3 lines of code in the function (the while busy/clearSCD/isStpbitset lines), I manage to get almost the correct output. EXCEPT, there is no Stop bit, and the first two writes sent out appear as is on the left. 

Hello Joushua,

Performing a brief overview of your initialization and write function, I don't see anything that necessarily stands out. Can you confirm that your SYSCLK is running at 90Mhz? This would be to confirm that your I2C module clock is set-up appropriately below:

    // I2CCLK = SYSCLK/(I2CPSC+1)
    // Prescaler - need 7-12 Mhz on module clk bitTimeLow = 10, bitTimeHigh = 5
    I2C_setupClock(obj->i2cHandle, 9, 76, 38);//I2C_PRESCALER, I2C_BITTIMELOW, I2C_BITTIMEHIGH);

I believe you are correct in seeing that everything is shifted to the right 1 bit in the set of data shown to the left. This seems to be caused by the SCL blip highlighted below, where an extra 0 bit is created:

Something is causing the SCL line to be brought low for a very short period of time. How often are you seeing this issue? The MCU should not be causing this since that is not a real SCL clock cycle (I.E. doesn't seem to match the clocking characteristics set or seen in other SCL cycles).

I'd suggest investigating this further, make sure your connections are all secure. Maybe even testing on a different I2C waveform analyzer if possible.

Hope this helps,

Kevin

Hello Kevin,

I managed to change the clock register values so they would produce a 50% High/ 50% Low time, and the cycle is at 100kHz, which I checked using my logic analyzer, so I do believe the board is running at 90MHz.

The SCL issue is very sporadic, and there is no real consistency to it. Sometimes it happens (and sometimes is "fixed") by turning the board off and then on. I've double checked to connections.

I went on the write a function that could read a single byte over I2C. The signal looked as expected, (Write, Sub_Addr+W, Restart, Sub_Addr+R, Data). Then the Start/Bit shift showed up again with it. BUT the data it was retrieving was still correct. That initially made me think it was an issue with my logic analyzer, but now that I think on it, I could see it being other possible issues as well, such as the slave device not seeing the short lived start condition due to timing requirements. I'll double check with a different logic analyzer and go from there.

Thanks for the suggestions!