TMS320F28375D: CLA read/write data issue

Konstantin Beloff

Part Number: TMS320F28375D

I am making a project using CLA to compute an FFT. The FFT code works pretty well on C28x, but when I put it in .cla file, the problems begin.

In the debugger if i do NOT manually "Connect target"&"Load symbols" to CLA, the debug simply can't excute the CLA part. (I use Cla1ForceTask1andWait(); from example projects).

If I Do connect and load, i step-by-step go through the CLA code, but it doesn't cause any changes in data! I tried replacing FFT with some basic operations with arrays, like change selected element, but this was of no use either. I could only see the values I loaded to the array in the main C28x code, but no changes could be done.

I did all the memory management in the .cmd file (code below), but I'm not that good in understanding how to write .cmd, so could have left out something crucial. Guess the problem is somewhere in this file, but I can't determine it.

Thanks in advance!

Regards, Konstantin


--define=CLA_C=1

#if CLA_C

//
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN           	: origin = 0x000000, length = 0x000002
   RAMM0           	: origin = 0x000122, length = 0x0002DE
   RAMD0           	: origin = 0x00B000, length = 0x000800
   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS0_1        : origin = 0x008000, length = 0x001000
   RAMGS0_2		   : origin = 0x00C000, length = 0x003000

   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   RAMGS11     : origin = 0x017000, length = 0x001000

   RESET           	: origin = 0x3FFFC0, length = 0x000002

PAGE 1 :

   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */

   CLA1_MSGRAMLOW  : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080

	RAMLS2_3 :    origin 0x009000, length 0x001000
	RAMLS4_5 : origin 0x00A000, length 0x001000

   RAMGS3_4		   : origin = 0x00F000, length = 0x002000
   RAMGS5_6		   : origin = 0x011000, length = 0x002000
   RAMGS7		   : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS12     : origin = 0x018000, length = 0x001000
   RAMGS13     : origin = 0x019000, length = 0x001000
   RAMGS14     		: origin = 0x01A000, length = 0x001000
   RAMGS15     		: origin = 0x01B000, length = 0x001000
}


SECTIONS
{
   codestart        : > BEGIN,     PAGE = 0
   
	#ifdef __TI_COMPILER_VERSION__
	   #if __TI_COMPILER_VERSION__ >= 15009000
	    .TI.ramfunc : {} > RAMM1,      PAGE = 0
	   #else
	   ramfuncs         : > RAMM0      PAGE = 0
	   #endif
	#endif

	CLAscratch :
	{ *.obj(CLAscratch)
	. += CLA_SCRATCHPAD_SIZE;
	*.obj(CLAscratch_end) } > RAMLS4_5, PAGE = 1

	Cla1Prog : > RAMLS4_5, PAGE =1

   .text            : >> RAMM0 | RAMM1 | RAMD0 | RAMD1 |RAMGS0_2
   /*RAMM0 | RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4*/,   PAGE = 0
   .cinit           : > RAMGS0_2,     PAGE = 0
   .pinit           : > RAMGS0_2,     PAGE = 0
   .switch          : > RAMGS0_2,     PAGE = 0
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   .stack           : > RAMGS3_4,     PAGE = 1
   .ebss            : > RAMGS8,    PAGE = 1
   .econst          : > RAMGS5_6,    PAGE = 1
   .esysmem         : > RAMGS7,    PAGE = 1

   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1

   .bss_cla		    : > RAMLS4_5,       PAGE = 1

//specific items
   IOBuffer          : > RAMLS2_3, ALIGN=512, PAGE=1 //2*256
 
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

over 7 years ago

0 Vivek Singh over 7 years ago

TI__Guru** 115271 points

Hi,

I noticed that you are using same LS RAM block (RAMLS4_5) for CLA program and data. I assume RAMLS4 and LS5 are configured as program RAM for CLA in your code (please confirm). Could you try placing the .bss_cla section and other data section like CLAscratch into RAML2_LS3 block (assuming LS2 and LS3 are programmed as CLA DATA RAM in your code, please confirm).

Regards,

Vivek Singh

0 Konstantin Beloff over 7 years ago in reply to Vivek Singh

Prodigy 230 points

void CLA_configClaMemory(void)
{
    extern uint32_t Cla1funcsRunStart, Cla1funcsLoadStart, Cla1funcsLoadSize;
    EALLOW;

    //
    // Initialize and wait for CLA1ToCPUMsgRAM
    //
    MemCfgRegs.MSGxINIT.bit.INIT_CLA1TOCPU = 1;
    while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1){};

    //
    // Initialize and wait for CPUToCLA1MsgRAM
    //
    MemCfgRegs.MSGxINIT.bit.INIT_CPUTOCLA1 = 1;
    while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1){};

    
    MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1;//shared btw cpu and cla1; if 0 - to cpu
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 1;//prog

    MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1;
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 1;

    MemCfgRegs.LSxMSEL.bit.MSEL_LS2 = 1;
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS2 = 0;//data

    MemCfgRegs.LSxMSEL.bit.MSEL_LS3 = 1;
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS3 = 0;

    MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1;
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 0;

    MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 1;
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 0;

    EDIS;
}

SECTIONS
{
   codestart        : > BEGIN,     PAGE = 0
   
	#ifdef __TI_COMPILER_VERSION__
	   #if __TI_COMPILER_VERSION__ >= 15009000
	    .TI.ramfunc : {} > RAMM1,      PAGE = 0
	   #else
	   ramfuncs         : > RAMM0      PAGE = 0
	   #endif
	#endif

	CLAscratch :
	{ *.obj(CLAscratch)
	. += CLA_SCRATCHPAD_SIZE;
	*.obj(CLAscratch_end) } > RAMLS2_3, PAGE = 1

	Cla1Prog : > RAMLS0_1, PAGE =0//

   .text            : >> RAMM0 | RAMM1 | RAMD0 | RAMD1 |RAMGS0_2
   /*RAMM0 | RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4*/,   PAGE = 0
   .cinit           : > RAMGS0_2,     PAGE = 0
   .pinit           : > RAMGS0_2,     PAGE = 0
   .switch          : > RAMGS0_2,     PAGE = 0
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   .stack           : > RAMGS3_4,     PAGE = 1
   .ebss            : > RAMGS8,    PAGE = 1
   .econst          : > RAMGS5_6,    PAGE = 1
   .esysmem         : > RAMGS7,    PAGE = 1

   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1

   .bss_cla		    : > RAMLS2_3,       PAGE = 1

//specific items
   IOBuffer          : > RAMLS4_5, ALIGN=512, PAGE=1 //2*256

Hi,

Thanks a lot, I reconfigured CLA program to LS0_1 on page 0 and therest of the LS blocks (2 to 5) are set and used as data blocks. Now the program at least executes CLA part. But now a different problem occured: I can't single-step CLA code, the error says that the Device is running, halt it and retry, but it is already halted, because i ran all the program in single step mode. The results of execution are far from expected, so debug is unavoidable, but I can't perform it due to this problem.

CPU1_CLA1: Can't Single Step Target Program: (Error -2060 @ 0x0) Requested operation cannot be done while device is running. Halt the device, and retry the operation. (Emulation package 7.0.48.0)

Regards,

Konstantin

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F28375D: CLA read/write data issue