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TMS320F28069: ADC Reading

Romano Pauli
Prodigy 30 points
Part Number: TMS320F28069


Hello all,

We are developing a power converter using the TMS320F28069 chip that is grid connected.  We have voltage sensors on the external and internal voltages.  We are seeing an issue where our internal sensors read back nice and clean while our external sensors will see a spike on one of the power legs.  The spike occurs at the peaks of the AC wave form. I first thought it was noise but we put an oscillator scope on the external voltages coming into the ADC pin and it comes back clean.

We changed the ADC buffer (switched channel 14 and 15 with channel 9 and 13) and got clean results on the AC waveform but then I noticed that the feedback that I swapped are now showing the irregularity in readings.  These seem to be the last 4 B-channels on the ADC mux.

As anyone else seen issues with those or other channels and what did you do to resolve it if you did?

  • 0
    TI__Guru 62975 points

    Romano,

    Can you check your ACQPS settings against the PCB characteristics and ADC input model?  The ADC channels can experience cross talk if the Ch cap is not given enough time to fully settle during the ACQPS window:

    -Tommy

  • 0 in reply to tlee
    Prodigy 30 points
    Hello Tommy,
    We are looking into the ACQPS and our timing. We are running a 60 kHz loop that is triggered by a PWM interrupt. This is the main interrupt that we are reading the ADC's in, I noticed that we had the ADC clock set to 90 Mhz but see in other forums that this could cause the ADC module to run out of spec. Is this true?

    Also we changed the setup so that ADCRESULT[9] now holds the voltage feedback that we saw the spikes on and ADCRESULT[13] now holds a different voltage feedback. The spikes stated with ADCRESULT[13] which points to cross talk specifically on those channels. Would you know why this would happen?

    Thanks for the assistance thus far.
  • 0 in reply to Romano Pauli
    TI__Guru 62975 points

    Romano,

    Yes, 90MHz is out of spec for the ADC clock.  You will probably want to set ADC clock to SYSCLK / 2.

    The S/H capacitor (Ch) is shared between ADC channels, and the capacitor will maintain residual charge between conversions.

    The recommended practice is to select an ACQPS window that is large enough so that the S/H capacitor can charge or discharge through a full-scale voltage swing and settle within your accuracy requirements.  This will mitigate the effects of cross talk from residual charge.

    A "less correct" method is to convert a fixed voltage (such as VSSA or VDDA) between your required SOCs so that the S/H cap is precharged to the same starting voltage every time.

    -Tommy

  • 0 in reply to tlee
    Prodigy 30 points
    Hello Tommy,

    Just so that I understand correctly. Since the Ch is shared in all the ADC channels if we had a channel that had a higher voltage say (2.8 volts) and then the next reading was a lower voltage (2.2) we could see some residual voltage and in effect get a higher reading then what we should. Hopefully I am understanding the correctly.

    Next I was looking through the errata and found the section concerning the Offset Self-Re-calibration Requirement. In this section it mentions that we should "perform the AdcOffsetSelfCal() function periodically with respect to temperature drift". Can you explain this a little bit more. Should we be monitoring the DSP temperature and call this function every delta temperature change?

    Also if we are not using the AdcOffsetSelfCal() at all does this still apply?
  • 0 in reply to Romano Pauli
    TI__Guru 62975 points

    Romano,

    Yes, you have the correct understanding for cross talk where Ch is concerned.

    The offset error for this ADC tends to be sensitive to board design and even ACQPS settings so it is recommended that you always perform your own offset calibration during initialization.  While running the application, you can recalibrate based on temperature movement or at a fixed time interval.  I would recommend using a fixed time interval for simplicity.  Here's a related discussion for reference.

    -Tommy