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TMS320F280049: ADC specification from SPRS945B?

AnBer
Mastermind 30625 points

Part Number: TMS320F280049

Team,

-Can you please confirm if the S&H ADC can be started at different time (ie asynchronously)?
The datasheet shows in "Table 5-48 ADC characteristics"  for "ENOB: VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1, asynchronous ADCs"  that it is not supported:

Q: Does it means that asynchronous is not supported at all or that we do not specify or test it? Can asynchronous mode be at all used and under what condition?

-The sampling capacitor seems to be much higher than for the previous devices:

Q: What are the benefit and drawback of having such an high Sampling capacitor value?

Thanks in advance,

Anthony

  • 0
    TI__Guru 60865 points
    Hi Anthony,

    The S+H capacitor is an abstraction of the ADC implementation (it isn't directly selected, but instead is a by-product of the ADC design). The ADC on this device is a SAR ADC, which uses a charge-redistribution capacitive DAC as one of it's primary components. The input signal is directly captured into this capacitor array, which naturally leads to a larger input capacitance vs. other ADC architectures (but also note that the effective input resistance is smaller than previous devices). While the input settling is admittedly a little slower than some previous designs, performance is significantly better in most key specifications (gain and offset error, linearity, and AC spec's like SNR and THD).

    Performance will degrade significantly on this device with asynchronously operating the ADCs. We don't recommend operating in this mode. To achieve datasheet performance, the user should ensure that the ADCs operate in lock-step when they are operating at the same time (S+H starts and ends at the same time, conversions start and end at the same time). The TRM section "Ensuring Synchronous Operation" goes into this is a little more depth.

    You might compare F28004x with how synchronous operation is specified on F2837xD and F2837xS devices. On these devices, we 'allow' synchronous operation (for some packages) and explicitly specify the expected performance degradation when operating this way.