TMS320F28335: NMI interrupt nesting

vesgine

Part Number: TMS320F28335

Hi,

I found a strange problem : the SEQ1INT will sometimes interrupt the NMI while NMI ISR is in progress, but it is not always happened.

I tried adding a "DINT" code at the beginning of the NMI ISR, but it doesn't work.

There is nothing code about interrupt prioritization or nesting in the NMI ISR.

Why?

over 8 years ago

0 Santosh Athuru over 8 years ago

TI__Mastermind 19810 points

Vesgine,
which NMI source is enabled? The CPU prioritization of interrupts is in Table 112 of device system control and interrupts user guide (www.ti.com/.../sprufb0d.pdf).

can you check the configuration to see if you have enabled GPIOXNMISEL for the GPIO to be taken as XNMI interrupt source and also enabled the XNMI in the XNMICR register? Also cross check you are not checking pre-emption of XINT1 or XINT2 with SEQ1INT?

Best Regards
Santosh Athuru

0 vesgine over 8 years ago in reply to Santosh Athuru

Expert 1315 points

I found the reason. The NMI ISR executed EINT by accident.
Thanks anyway!

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TMS320F28335: NMI interrupt nesting