DBRED, DBFED registers are not shadowed. If these registers are updated radomly regards to TBCTR, will the PWM be interrupted? I am confused about this.
There is no such evidence showing it is OK(the PWM will not interrupted). But I run the following test codes. It seems to be OK.
//----------------------------------------------
if(++u16Timer<3000u){
EPwm1Regs.DBFED = EPwm1Regs.DBRED = 0;
GpioDataRegs.GPACLEAR.bit.GPIO18 = 1;}
else{
EPwm1Regs.DBFED = EPwm1Regs.DBRED = 60;
GpioDataRegs.GPASET.bit.GPIO18 = 1;}
//------------------------------------------PS：(Active High, Complementary; OUT_MODE = DB_FULL_ENABLE)
The test result shows that the DB will be either 60 or 0 system clock periods. That is just what I need.
However it is only the test result without any theory or hardware guide. Will anyone elaborates about this?
Thanks in advance.
