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TMS320F280049: ADC Acquisition Window Duration Calculation

Linda Zhang84708
Expert 6860 points
Part Number: TMS320F280049


Hello Champs,

In F280049 TRM Chapter 10.3.2, there is below description for "Choosing an Acquisition Window Duration":

For correct operation, the input signal to the ADC must be allowed adequate time to charge the sample and hold capacitor, Ch. Typically, the S+H duration is chosen such that the sampling capacitor will be charged to within ½ LSB or ¼ LSB of the final value, depending on tolerable settling error. A rough approximation of the required sampling time can be determined using a first-order RC model with R = Rs + Ron and C = Ch. The RC time constant is then (Rs + Ron)∙(Ch).

Question 1: Why "the S+H duration is chosen such that the sampling capacitor will be charged to within ½ LSB or ¼ LSB of the final value"?

Question 2: If the sample and hold window duration for ADC is calculated using the equation in this chapter according to the designed circuit, the ACQPS value should at least be equal or be bigger than this calculated value, is it right?

Would you please kindly help? Thanks!

Best Regards,

Linda

  • 0
    TI__Mastermind 39620 points

    Hi Linda,

    Please see responses below:

    Question 1: Why "the S+H duration is chosen such that the sampling capacitor will be charged to within ½ LSB or ¼ LSB of the final value"?

    - You would want to have the sampling capacitor settle to a value that is as close as possible to the level of the input signal.  During quantization, the smallest value that a signal can be compared with is 1 LSB unit.  LSB is the ADCs resolution.  Comparing the input signal to a the 1 LSB smallest resolution would ensure you that the results would be within the smallest ADC resolution, hence 1/4 or 1/2 LSB settling is recommended.  Of course, you can choose higher charging levels of the sampling capacitor and shorten the sampling time if you want to improve throughput, but this increases your conversion errors as you are allowing the ADC to digitize the data even if the input signal level has not fully charged the sampling capacitor.  On the other hand, you can increase the charging time of the sampling capacitor to be equal to the input signal level but due to the exponential curve or RC charging, this would require longer S+H and degrade the ADC throughput.  A good rule of thumb in ADC sampling is to allow the sampling capacitor to charge to within 1/2 to 1/4 LSB - this way you ensure that the ADc is producing reliable conversion results with the proper sampling times.

    Question 2: If the sample and hold window duration for ADC is calculated using the equation in this chapter according to the designed circuit, the ACQPS value should at least be equal or be bigger than this calculated value, is it right?

    - Yes, you are correct.  The calculated ACQPS should be greater than or equal to the calculated value.

    Please let me know if you have any other questions regarding this topic.

    Best regards,

    Joseph